Never mind, setting STRICT_ALIGNMENT to zero did the trick.
- Jamie
----- Original Message ----
> From: Jamie Prescott <jpre...@yahoo.com>
> To: gcc@gcc.gnu.org
> Sent: Saturday, May 9, 2009 1:20:28 PM
> Subject: Avoid subreg access patterns
>
>
> Sorry for the newbie question, but I don't seem to get around it.
> The backend I'm writing has 32 bit registers, and 64 bit registers (used for
> SF,
> DF, DI).
> There is a direct store instruction from a 64 bit register, to memory, and
> this
> instruction is correctly
> seen and used by GCC in other occasions.
> Nevertheless GCC generate a split 32 bit store, with subreg access.
> Is there a way to prevent GCC to perform split/subreg accesses?
>
> struct mooma {
> double a, b;
> };
>
>
> extern int vva(int k, ...);
>
> int cvva(int u)
> {
> struct mooma mm;
>
> mm.a = u - 1;
> mm.b = 0;
>
> return vva(u - 2, mm);
> }
>
>
> ;; Function cvva (cvva)
>
> Partition 0: size 16 align 4
> mm, offset 0
>
> ;; Generating RTL for tree basic block 2
>
> ;; mm.a = (double) (u + -1)
> (insn 6 5 7 wwww.c:44 (set (reg:SI 126)
> (const_int -1 [0xffffffffffffffff])) -1 (nil))
>
> (insn 7 6 8 wwww.c:44 (set (reg:SI 125)
> (plus:SI (reg/v:SI 124 [ u ])
> (reg:SI 126))) -1 (nil))
>
> (insn 8 7 9 wwww.c:44 (set (reg:DF 127)
> (float:DF (reg:SI 125))) -1 (nil))
>
> (insn 9 8 10 wwww.c:44 (set (mem/s/c:SI (plus:SI (reg/f:SI 118
> virtual-stack-vars)
> (const_int -16 [0xfffffffffffffff0])) [0+0 S4 A32])
> (subreg:SI (reg:DF 127) 0)) -1 (nil))
>
> (insn 10 9 0 wwww.c:44 (set (mem/s/c:SI (plus:SI (reg/f:SI 118
> virtual-stack-vars)
> (const_int -12 [0xfffffffffffffff4])) [0+4 S4 A32])
> (subreg:SI (reg:DF 127) 4)) -1 (nil))
>
> ;; mm.b = 0.0
> (insn 11 10 12 wwww.c:45 (set (mem/s/c:SI (plus:SI (reg/f:SI 118
> virtual-stack-vars)
> (const_int -8 [0xfffffffffffffff8])) [0+0 S4 A32])
> (const_int 0 [0x0])) -1 (nil))
>
> (insn 12 11 0 wwww.c:45 (set (mem/s/c:SI (plus:SI (reg/f:SI 118
> virtual-stack-vars)
> (const_int -4 [0xfffffffffffffffc])) [0+4 S4 A32])
> (const_int 0 [0x0])) -1 (nil))
>
>
>
> The movdf instruction is defined as (the 'x' regclass maps the 64 bit
> registers):
>
> (define_insn "movdf"
> [(set (match_operand:DF 0 "nonimmediate_operand" "=x,x,m")
> (match_operand:DF 1 "general_operand" "m,x,x"))]
> ""
> "@
> ldr.f\t%1,%0
> fdmov\t%1,%0
> str.f\t%1,%0"
> [
> (set_attr "length" "3,6,3")
> (set_attr "cc" "none,none,none")
> ]
> )
>
>
> Since this instruction set does not have a direct move of 64 bit constant to
> register, I defined
> this:
>
> enum reg_class
> js1_preferred_reload_class(rtx x, enum reg_class regclass)
> {
> enum machine_mode mode = GET_MODE(x);
>
> if (regclass == NO_REGS ||
> ((GET_CODE(x) == CONST_INT ||
> GET_CODE(x) == CONST_DOUBLE) && regclass == X_REGS))
> return NO_REGS;
>
> return GET_MODE_SIZE(mode) > 4 ? NO_REGS: regclass;
> }
>
>
> Is this the problem?
> Thank you,
>
> - Jamie
