define_peephol2 insn

[M R Swami Reddy]

Hello,

I have ported gcc to a 16-bit target. Now problem is, gcc generates wrong code 
with -O1 and above optimization for move and load/store instructions, b using
the 32-bit registers with 16-bit instructions. For ex:
===
move r13, r1 // move 0-15 bit to r1 register
move r13, r0 // move 16-31 bits to r0 register, but this move performs
             // only 0-15 bits to r0 registers, which NOT INTENDED.
To solve the above issue, can I use the "define_peephole2" insn pattern?

[like: movd r13, (r1,r0) // move r13 0-31 bits r1,r0 registers. Note:
r1 and r0 are 16-bits registers]

Please advise.

Any comments or suggestions most welcome.

Thanks in advance.

Thanks
Swami