raja.sal...@iap-online.com writes: >>> Is there a way to make the instruction has to allocate to run without >>> using the scheduler for particular instruction ? >> >> I don't understand the question. > > The target we are using supports parallel instruction execution, Max 7. > For one cycle, one instruction packet is executed. one packet has max 7 > instructions. so the scheduler is enabled. However, the scheduler enabling > is not required for some packets. so how we can disable the instruction > scheduling for particular packets ?
The scheduler in gcc schedules individual machine instructions. Are you asking about disabling the scheduler from the source code, or are you asking about disabling the scheduler for specific instructions? If you are talking about specific instructions, then you just need to give them appropriate characteristics. For example, if an instruction is defined to use all the functional units, then it will not be scheduled in any very meaningful way. Note that gcc's scheduler is not really VLIW aware, and if there are any constraints on the instructions to put them into a packet those will have to be implemented in C code in your backend. This is not a simple task, but it has been done for some targets, such as the FRV. >> Nothing is out of scope of the scheduler. Using unspec_volatile in >> the RTL template makes the instruction a scheduling barrier and a >> memory barrier. > > Can you give more information or link to understand more about > unspec_volatile ? The information available in gcc internals is not > sufficient. I don't know what to say beyond what is already in the internals documentation. I don't know of any more detailed documentation. If you ask a more specific question then perhaps somebody can answer it. Ian
