On Wed, Sep 3, 2008 at 6:09 PM, David Edelsohn <[EMAIL PROTECTED]> wrote: > On Wed, Sep 3, 2008 at 6:53 PM, Anton Blanchard <[EMAIL PROTECTED]> wrote: >> The only thing lwsync wont order is a store followed by a load. Since >> the lwsync will always be paired with a store (the stwcx), we will order >> all accesses before it and provide a release barrier. > > Anton, > > My one other concern is developers using the builtins for applications on > embedded PowerPC processors. lwsync will not order accesses to device > memory space, AFAICT. I do not know if developers would rely on GCC builtins > in that context and assume it implements the correct semantics. Otherwise, > I agree that the memory barrier operations probably can use lwsync.
Would it be possible to have a conservative default and use a more optimal form based on a specific CPU specified by -mcpu=? I was thinking of doing something similar on MIPS where there are similar issues. David Daney
