On Thu, Jul 3, 2008 at 4:13 PM, Tianwei <[EMAIL PROTECTED]> wrote:
> On Thu, Jul 3, 2008 at 3:26 PM, Steven Bosscher <[EMAIL PROTECTED]> wrote:
>> On Fri, Jul 4, 2008 at 12:05 AM, Tianwei <[EMAIL PROTECTED]> wrote:
>>> Hi, all,
>>> My current project wants to reuse DDG's infrastructure to get some
>>> loop carried dependency information, I debug these code for a while,
>>> but have some questions, Hope you can
>>> give me some suggestions.
>>>
>>> 1. my platform is X86, and gcc version is 4.3.1, when i use -fsms,
>>> and debug the code, found that for the following code, if always
>>> return NULL_RTX:
>>>
>>> /* Make sure this is a doloop. */
>>> if ( !(count_reg = doloop_register_get (head, tail)))
>>> {
>>> if (dump_file)
>>> fprintf (dump_file, "SMS doloop_register_get failed\n");
>>> continue;
>>> }
>>>
>>> when I check the doloop_register_get, and found that it's guarded by a
>>> ifdef "HAVE_doloop_end", even i make clobber the whole compiler,
>>> rebuild the compiler by "CFLAGS='-DHAVE_doloop_end'", it still will
>>> complain error, can't find the gen_doloop_end.
>>>
>>> so the first question is: does SMS is support on X86?
>>
>> No. the x86 backend has no doloop insn pattern. To see what that
>> means, see loop-doloop.c, and look for doloop in
>> http://gcc.gnu.org/onlinedocs/gccint/Standard-Names.html.
>>
>> Gr.
>> Steven
>>
> Steven, thanks very much. I will look at it.
> BTW, now the ddg construction seems to do the following step:
> 1. compuate the intra-dependency accoring to scheduler dependency analysis
> 2. during the intra-dependency function, it will also perform
> inter-loop-mem-dep
also now for this inter-loop-mem-dep, it's very conservative, it will
simply assume that
if one mem instruction modified the memory, then there will be an edge
to any insns that access mem
/* If this insn modifies memory, add an edge to all insns that access
memory. */
if (mem_access_insn_p (dest_node->insn))
{
int j;
for (j = 0; j <= i; j++)
{
ddg_node_ptr j_node = &g->nodes[j];
if (mem_access_insn_p (j_node->insn))
/* Don't bother calculating inter-loop dep if an intra-loop dep
already exists. */
if (! TEST_BIT (dest_node->successors, j))
add_inter_loop_mem_dep (g, dest_node, j_node);
}
}
/* Given two nodes, analyze their RTL insns and add inter-loop mem deps
to ddg G. */
static void
add_inter_loop_mem_dep (ddg_ptr g, ddg_node_ptr from, ddg_node_ptr to)
{
if (mem_write_insn_p (from->insn))
{
if (mem_read_insn_p (to->insn))
create_ddg_dep_no_link (g, from, to, TRUE_DEP, MEM_DEP, 1);
else if (from->cuid != to->cuid)
create_ddg_dep_no_link (g, from, to, OUTPUT_DEP, MEM_DEP, 1);
}
else
{
if (mem_read_insn_p (to->insn))
return;
else if (from->cuid != to->cuid)
{
create_ddg_dep_no_link (g, from, to, ANTI_DEP, MEM_DEP, 1);
create_ddg_dep_no_link (g, to, from, TRUE_DEP, MEM_DEP, 1);
}
}
}
it won't query the aliaser for more precise information, maybe the
code is a little older.
> 3. then it will use another pass to perform inter-loop-reg-dep.
> i will debug some testcase to understand why it did in this
> way(especially why inter-loop-mem is embedded in intra-dependency
> phase), how it can guarantee we won't miss any dependency.
>
> Tianwei
>
