Hello all,
For the big endian 16bit target that i am porting to gcc 4.1.2 a nop
is needed after a load instruction if the destination register of the
load instruction is used as the source in the next instruction. So
load R0, R3[2]
add R2, R0
needs a nop inserted in between the instructions. I have issues when
the operation is that of 32bit data types. The target doesn't have any
32bit instructions. All the 32bit move instructions are split after
reload. The following is an example where i am having issues
(set (reg:HI 2 R2)
(mem/s:HI (reg/f:HI 8 R8)
(set (reg:HI 3 R3)
(mem/s:HI (plus:HI (reg/f:HI 8 R8)
(const_int 2 [0x2]))
(set (reg:SI 0 R0)
(minus:SI (reg:SI 0 R0)
(reg:SI 2 R2)))
load R2, R8
load R3, R8[2]
sub R1, R3
subc R0, R2
For the above case no nop inserted. But because of the endianess src
reg gets used in the next instructions. How do i solve this?
I do nop insertion in reorg pass where i first do delay slot
scheduling. The follwoing is what i have in reorg() for nop insertion
attr = get_attr_type (insn);
if (next_insn && attr == TYPE_LOAD) {
if (insn_true_dependent_p (insn, next_insn))
emit_insn_after (gen_nop (), insn);
}
........
static bool
insn_true_dependent_p (rtx x, rtx y)
{
rtx tmp;
if (! INSN_P (x) || ! INSN_P (y))
return 0;
tmp = PATTERN (y);
note_stores (PATTERN (x), insn_dependent_p_1, &tmp);
return (tmp == NULL_RTX);
}
static void
insn_dependent_p_1 (rtx x, rtx pat ATTRIBUTE_UNUSED, void *data)
{
rtx * pinsn = (rtx *) data;
if (*pinsn && reg_mentioned_p (x, *pinsn))
*pinsn = NULL_RTX;
}
I think apart from the above cases i will also have cases where nop
gets inserted when it's not really required.
How will it be possible to solve this issue?
Regards,
Shafi
