David Edelsohn wrote:
I would prefer feature-based.
TARGET_HARD_FLOAT represents the presence of FPUs.
TARGET_FPRS represents the presence of FP register set because
one variant used GPRs for FP operations.
E500 then added another variant with double-precision FP in the
GPRs.
How about this:
(define_expand "negdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "")
(neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
"")
For an instruction supported on all variants (both BookE and E500)
with a double precision FPU.
(define_expand "negsf2"
[(set (match_operand:SF 0 "gpc_reg_operand" "")
(neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
"TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
"")
For an instruction supported on all variants with a
single precision FPU or a double precision FPU which
supports single precision operations.
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
(float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
"TARGET_POWERPC64 &&
TARGET_HARD_FLOAT &&
(TARGET_FPRS && TARGET_DOUBLE_FLOAT)"
"fcfid %0,%1"
[(set_attr "type" "fp")])
for an instruction supported on BookE only with double
precision FPU.
(define_insn "*subsf3_gpr"
[(set (match_operand:SF 0 "gpc_reg_operand" "=r")
(minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
(match_operand:SF 2 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT &&
(!TARGET_FPRS && TARGET_SINGLE_FLOAT)"
"efssub %0,%1,%2"
[(set_attr "type" "fp")])
for an instruction on E500 only with single precision FP.
(define_insn "fixuns_truncdfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
"TARGET_HARD_FLOAT &&
(!TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"efdctuiz %0,%1"
[(set_attr "type" "fp")])
for an instruction on E500 only with double precision FP.
--
Michael Eager [EMAIL PROTECTED]
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
