On Thu, Apr 3, 2008 at 6:49 PM, Ian Lance Taylor <[EMAIL PROTECTED]> wrote: > > "Mohamed Shafi" <[EMAIL PROTECTED]> writes: > > > It is not necessary that a pattern with a single constrain will have > > only one instruction in the template. > > Say if the pattern A have two instructions in the template and pattern > > B has one instruction in the template and the target has only two > > delay slots will i be able to tell gcc that if delay slot 1 is filled > > with pattern A then don't fill the delay slot 2? > > If I understand the question, then the answer is yes: write two > different define_delay patterns, one for instructions that match > pattern A and one for instructions that match pattern B. > I think you got it wrong. Say the target has two delay slots for call instructions. So we can have something like this (define_attr "slottable" "no,yes,has_slot" (const_string "yes"))
(define_delay (eq_attr "slottable" "has_slot") [(eq_attr "slottable" "yes") (nil) (nil) (eq_attr "slottable" "yes") (nil) (nil)]) So in define_insn for call i can have (set_attr "slottable" "has_slot") Now imagine that i have 3 patterns : Pattern A with two instructions in its template, Pattern B and Pattern C with only one instruction in its template. When it comes to filling the call instruction delay slot if slot 1 is filled with Pattern A then there is no need to fill slot 2. But if its filled with Pattern C or Pattern B, then slot 2 should be filled with Pattern B or Pattern C, but not Pattern A. Will i be able to do this in the back-end? Regards, Shafi
