Hello,
In porting GCC (still 4.2) to our VLIW processor, I tried to model
pipeline as precisely as possible. If I only model the issue slot
resource, it is fine. GCC generates a small state machine and compiles
code quickly.
However, if I also want to model the resource for writing back register
file, the number of states and arcs just explodes. It is especially true
for long pipeline instruction. In the following example,
(define_insn_reservation "mul_op" 8
(and (eq_attr "type" "mul")
(eq_attr "dual" "no"))
"long_p0|long_p1, nothing * 7")
50 NDFA states, 178 NDFA arcs
50 DFA states, 178 DFA arcs
50 minimal DFA states, 178 minimal DFA arcs
(define_insn_reservation "mul_op" 8
(and (eq_attr "type" "mul")
(eq_attr "dual" "no"))
"long_p0|long_p1, nothing * 6, port_0")
7680 NDFA states, 27008 NDFA arcs
7680 DFA states, 27008 DFA arcs
7680 minimal DFA states, 27008 minimal DFA arcs
The number of states and arcs increases dramatically for just single
difference. Modeling other instructions in a similar way becomes
impossible therefore. It takes forever to build GCC.
What I did wrong here? I just want to model resource usage in issue
slot and writeback stage in order possible stall cycle. What is the
cheap to do this? Thanks in advance.
Cheers,
Bingfeng Mei
Broadcom UK
