Hi,
Moving on the SPARC, I see a lot of similar
unsupported instruction failures. I only
see a single sparc feature test. It is for
"-multrasparc -mvis" and it is actually
passing on the sparc instruction simulator in
gdb. It doesn't make me feel good that this
part passes since I thought SIS was a vanilla
V7 simulator. I think this test isn't tight enough:
proc check_effective_target_ultrasparc_hw { } {
return [check_runtime ultrasparc_hw {
int main() { return 0; }
} "-mcpu=ultrasparc"]
}
For sure though, SIS does NOT support VIS and
there is no test for that. This leads to this:
Starting program:
/home/joel/work-gnat/svn/b-gcc1-sparc/gcc/testsuite/gcc/pr18400.exe
Unexpected trap (0x 2) at address 0x02001318
illegal instruction
Program exited normally.
(gdb) disassemble 0x02001318
Dump of assembler code for function check_vect:
...
0x02001318 <check_vect+20>: impdep1 62, %g0, %g0, %g0
...
Can someone familiar with VIS provide an instruction
that is OK to do a run-time test with to check if
it is supported?
This appears to be the root of as high as ~80% of
sparc-rtems4.9 test failures.
Thanks.
--
Joel Sherrill, Ph.D. Director of Research & Development
[EMAIL PROTECTED] On-Line Applications Research
Ask me about RTEMS: a free RTOS Huntsville AL 35805
Support Available (256) 722-9985
