Hello,
I think you should look at the constraint of the instruction in your md
file, for example (taken from altivec.md file under config/rs6000 dir):
(define_insn "altivec_stvx"
[(parallel
[(set (match_operand:V4SI 0 "memory_operand" "=Z")
(match_operand:V4SI 1 "register_operand" "v"))
(unspec [(const_int 0)] UNSPEC_STVX)])]
"TARGET_ALTIVEC"
"stvx %1,%y0"
[(set_attr "type" "vecstore")])
The v and Z indicate constraints on the operands of the instruction.
Their description can be found in constraints.md file in the same dir::
(define_memory_constraint "Z"
"Indexed or indirect memory operand"
(match_operand 0 "indexed_or_indirect_operand"))
You can take a look at the gcc internals for more info about this.
Revital
[EMAIL PROTECTED] wrote on 07/12/2007 00:52:38:
> Hello Everyone,
> I am trying to modify the OpenRISC GCC to modify the existing
> instructions and add more instructions into the system. I had to rewrite
> most of the or32.md. When I am trying to compile something, it says the
> following constaint is not found. Can someone please help me with
> reading this contraint correctly?
>
> (insn 112 110 478 12 (set (mem:QI (reg/v/f:SI 16 r16 [orig:72 line.183 ]
> [72]) [0 S1 A8])
> (const_int 0 [0x0])) 16 {movqi} (nil)
> (nil))
>
> From what I see, it is just a that we are trying to set 1 byte of a
> memory location with the value in register #16 (r16) with an offset of
> 0....which I have handled already in my machine description...so what
> can this be?
>
> Any help is highly appreciated.
>
> Thanking You,
>
> Yours Sincerely,
>
> Balaji V. Iyer.
>
> --
>
> Balaji V. Iyer
> PhD Student,
> Center for Efficient, Scalable and Reliable Computing,
> Department of Electrical and Computer Engineering,
> North Carolina State University.
>
>
