Simple way to write almost same pattern?

[Bingfeng Mei]

Hi,

I am writing instruction patterns for vector modes (V4Si, V8HI, V16QI,
etc).  Since these modes have the same length, the underlying
instructions may also be the same (load/store instrucitons,  AND/OR
instructions, etc).  Is there any simple way to combines patterns for
different modes instead of writing the following code?  A simple form
should be more maintainable.


(define_expand "andv4si3"
  [(set (match_operand:V4SI         0 "register_operand"  "=r")
        (and:SI (match_operand:V4SI 1 "register_operand" "r")
                (match_operand:V4SI 2 "general_operand" "ri")))]
 ""
 "andl %0, %1, %2"

(define_expand "andv8hi3"
  [(set (match_operand:V8HI         0 "register_operand"  "=r")
        (and:SI (match_operand:V8HI 1 "register_operand" "r")
                (match_operand:V8HI 2 "nonmemory_operand" "ri")))]
 ""
 "andl %0, %1, %2"


(define_expand "andv16qi3"
  [(set (match_operand:V16QI         0 "register_operand"  "=r")
        (and:SI (match_operand:V16QI 1 "register_operand" "r")
                (match_operand:V16QI 2 "nonmemory_operand" "ri")))]
 ""
 "andl %0, %1, %2"
...

Thanks,

Bingfeng Mei
Broadcom UK