On 9/12/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote: > Tehila asked me a while ago to comment based on my experience with the > RTL if convert pass and the discussions some of us had at the GCC > summit. Sorry it took me so long to respond. > > The target I care about (Cell SPU) has some things that make an > aggressive if convert very useful and profitable. It has conditional > moves for every mode (there is a single, unified register file), never > traps on illegal addresses (addresses always wrap to the 256KB address > space), and branches are expensive (there is no hardware cache). > > The main limitation with the RTL if-convert pass is that it only > recognizes specific patterns. It is easy to write a complicated if > statement (just using normal C with &&/||) that would never get > converted because it ends up with basic blocks that have many in edges > that if-convert generally doesn't handle. (In our internal tree we > modified the RTL pass to handle some cases of multiple in-edges, and can > handle any number of insns in a basic block.) > > I haven't looked at the tree-SSA if-convert code yet, but based on what > was described to me at the summit it seemed to be taking the same > approach as the RTL pass. Recognize certain patterns and convert it. > > I would like to see an approach that is able to take an arbitrary flow > graph without backedges and convert it to straight line code, limited > only by the cost model and impossible cases (e.g., inline asm).
We now have (yet another) pass that looks at multiple basic blocks to catch if-conversion opportunities in &&/|| sequences, tree-ssa-ifcombine.c, which of course also handles certain special patterns. There is also some old patches of mine attached to PR22568 to improve RTL ifcvt to handle multi-basic-block conditional move sequences. Richard.
