On Tue, 21 Aug 2007, Ian Lance Taylor wrote:
With the modifications I made, GCC still compiled fine. However,
libgcc and libstdc++ DO still get build with the missing instructions
(according to objdump -D). Why is that? Is that a consequence of the
ADA files? Or something else? Where should I look? Is the it ada files
that are the cause of the problem I'm seeing?
It must be something else. I'm not sure what, though. It might be
something as simple as an instruction built from substrings. For
example, search for altivec_vmsumu<VI_char>m in altivec.md.
I just re-checked for that and I can't find any. I have attached a diff
for my modified altivec.h, altivec.md and rs6000.c files. Patch in
gcc/config/rs6000 subtree with -p1.
Can anyone think of anywhere else I should be looking? Where else could
these instructions be coming from?
Thanks.
Gordan
diff -uN altivec/altivec.h vmx128/altivec.h
--- altivec/altivec.h 2007-08-22 09:31:46.000000000 +0100
+++ vmx128/altivec.h 2007-08-22 09:31:21.000000000 +0100
@@ -71,9 +71,6 @@
#define vec_lvxl vec_ldl
#define vec_vlogefp vec_loge
#define vec_vmaddfp vec_madd
-#define vec_vmhaddshs vec_madds
-#define vec_vmladduhm vec_mladd
-#define vec_vmhraddshs vec_mradds
#define vec_vnmsubfp vec_nmsub
#define vec_vnor vec_nor
#define vec_vor vec_or
@@ -94,8 +91,6 @@
#define vec_stvx vec_st
#define vec_stvxl vec_stl
#define vec_vsubcuw vec_subc
-#define vec_vsum2sws vec_sum2s
-#define vec_vsumsws vec_sums
#define vec_vrfiz vec_trunc
#define vec_vxor vec_xor
@@ -142,20 +137,6 @@
#define vec_vminsh __builtin_vec_vminsh
#define vec_vminsb __builtin_vec_vminsb
#define vec_mradds __builtin_vec_mradds
-#define vec_vmsumshm __builtin_vec_vmsumshm
-#define vec_vmsumuhm __builtin_vec_vmsumuhm
-#define vec_vmsummbm __builtin_vec_vmsummbm
-#define vec_vmsumubm __builtin_vec_vmsumubm
-#define vec_vmsumshs __builtin_vec_vmsumshs
-#define vec_vmsumuhs __builtin_vec_vmsumuhs
-#define vec_vmulesb __builtin_vec_vmulesb
-#define vec_vmulesh __builtin_vec_vmulesh
-#define vec_vmuleuh __builtin_vec_vmuleuh
-#define vec_vmuleub __builtin_vec_vmuleub
-#define vec_vmulosh __builtin_vec_vmulosh
-#define vec_vmulouh __builtin_vec_vmulouh
-#define vec_vmulosb __builtin_vec_vmulosb
-#define vec_vmuloub __builtin_vec_vmuloub
#define vec_nmsub __builtin_vec_nmsub
#define vec_packpx __builtin_vec_packpx
#define vec_vpkswss __builtin_vec_vpkswss
@@ -173,9 +154,6 @@
#define vec_vsubshs __builtin_vec_vsubshs
#define vec_vsubsbs __builtin_vec_vsubsbs
#define vec_sum4s __builtin_vec_sum4s
-#define vec_vsum4shs __builtin_vec_vsum4shs
-#define vec_vsum4sbs __builtin_vec_vsum4sbs
-#define vec_vsum4ubs __builtin_vec_vsum4ubs
#define vec_sum2s __builtin_vec_sum2s
#define vec_sums __builtin_vec_sums
#define vec_trunc __builtin_vec_trunc
diff -uN altivec/altivec.md vmx128/altivec.md
--- altivec/altivec.md 2007-08-22 09:31:46.000000000 +0100
+++ vmx128/altivec.md 2007-08-22 09:31:21.000000000 +0100
@@ -566,53 +566,6 @@
;; [(set (match_operand:V4SI 0 "register_operand" "=v")
;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
;; (match_operand:V4SI 2 "register_operand" "v")))]
-(define_expand "mulv4si3"
- [(use (match_operand:V4SI 0 "register_operand" ""))
- (use (match_operand:V4SI 1 "register_operand" ""))
- (use (match_operand:V4SI 2 "register_operand" ""))]
- "TARGET_ALTIVEC"
- "
- {
- rtx zero;
- rtx swap;
- rtx small_swap;
- rtx sixteen;
- rtx one;
- rtx two;
- rtx low_product;
- rtx high_product;
-
- zero = gen_reg_rtx (V4SImode);
- emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
-
- sixteen = gen_reg_rtx (V4SImode);
- emit_insn (gen_altivec_vspltisw (sixteen, gen_rtx_CONST_INT (V4SImode,
-16)));
-
- swap = gen_reg_rtx (V4SImode);
- emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen));
-
- one = gen_reg_rtx (V8HImode);
- convert_move (one, operands[1], 0);
-
- two = gen_reg_rtx (V8HImode);
- convert_move (two, operands[2], 0);
-
- small_swap = gen_reg_rtx (V8HImode);
- convert_move (small_swap, swap, 0);
-
- low_product = gen_reg_rtx (V4SImode);
- emit_insn (gen_altivec_vmulouh (low_product, one, two));
-
- high_product = gen_reg_rtx (V4SImode);
- emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
-
- emit_insn (gen_altivec_vslw (high_product, high_product, sixteen));
-
- emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
-
- DONE;
- }")
-
;; Fused multiply subtract
(define_insn "altivec_vnmsubfp"
@@ -644,38 +597,6 @@
"vmsumm<VI_char>m %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
-(define_insn "altivec_vmsumshm"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")
- (match_operand:V4SI 3 "register_operand" "v")]
- UNSPEC_VMSUMSHM))]
- "TARGET_ALTIVEC"
- "vmsumshm %0,%1,%2,%3"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmsumuhs"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")
- (match_operand:V4SI 3 "register_operand" "v")]
- UNSPEC_VMSUMUHS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
- "TARGET_ALTIVEC"
- "vmsumuhs %0,%1,%2,%3"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmsumshs"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")
- (match_operand:V4SI 3 "register_operand" "v")]
- UNSPEC_VMSUMSHS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
- "TARGET_ALTIVEC"
- "vmsumshs %0,%1,%2,%3"
- [(set_attr "type" "veccomplex")])
-
;; max
(define_insn "umax<mode>3"
@@ -726,38 +647,6 @@
"vminfp %0,%1,%2"
[(set_attr "type" "veccmp")])
-(define_insn "altivec_vmhaddshs"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")
- (match_operand:V8HI 3 "register_operand" "v")]
- UNSPEC_VMHADDSHS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
- "TARGET_ALTIVEC"
- "vmhaddshs %0,%1,%2,%3"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmhraddshs"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")
- (match_operand:V8HI 3 "register_operand" "v")]
- UNSPEC_VMHRADDSHS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
- "TARGET_ALTIVEC"
- "vmhraddshs %0,%1,%2,%3"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmladduhm"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")
- (match_operand:V8HI 3 "register_operand" "v")]
- UNSPEC_VMLADDUHM))]
- "TARGET_ALTIVEC"
- "vmladduhm %0,%1,%2,%3"
- [(set_attr "type" "veccomplex")])
-
(define_insn "altivec_vmrghb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1
"register_operand" "v")
@@ -924,79 +813,6 @@
"vmrglw %0,%1,%2"
[(set_attr "type" "vecperm")])
-(define_insn "altivec_vmuleub"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")]
- UNSPEC_VMULEUB))]
- "TARGET_ALTIVEC"
- "vmuleub %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmulesb"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")]
- UNSPEC_VMULESB))]
- "TARGET_ALTIVEC"
- "vmulesb %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmuleuh"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")]
- UNSPEC_VMULEUH))]
- "TARGET_ALTIVEC"
- "vmuleuh %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmulesh"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")]
- UNSPEC_VMULESH))]
- "TARGET_ALTIVEC"
- "vmulesh %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmuloub"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")]
- UNSPEC_VMULOUB))]
- "TARGET_ALTIVEC"
- "vmuloub %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmulosb"
- [(set (match_operand:V8HI 0 "register_operand" "=v")
- (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V16QI 2 "register_operand" "v")]
- UNSPEC_VMULOSB))]
- "TARGET_ALTIVEC"
- "vmulosb %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmulouh"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")]
- UNSPEC_VMULOUH))]
- "TARGET_ALTIVEC"
- "vmulouh %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vmulosh"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")]
- UNSPEC_VMULOSH))]
- "TARGET_ALTIVEC"
- "vmulosh %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-
;; logical ops
(define_insn "and<mode>3"
@@ -1219,46 +1035,6 @@
"vsro %0,%1,%2"
[(set_attr "type" "vecperm")])
-(define_insn "altivec_vsum4ubs"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")]
- UNSPEC_VSUM4UBS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
- "TARGET_ALTIVEC"
- "vsum4ubs %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vsum4s<VI_char>s"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")]
- UNSPEC_VSUM4S))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
- "TARGET_ALTIVEC"
- "vsum4s<VI_char>s %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vsum2sws"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")]
- UNSPEC_VSUM2SWS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
- "TARGET_ALTIVEC"
- "vsum2sws %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-(define_insn "altivec_vsumsws"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")]
- UNSPEC_VSUMSWS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
- "TARGET_ALTIVEC"
- "vsumsws %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
(define_insn "altivec_vspltb"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(vec_duplicate:V16QI
@@ -2065,48 +1841,6 @@
DONE;
}")
-(define_insn "altivec_vsumsws_nomode"
- [(set (match_operand 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")]
- UNSPEC_VSUMSWS))
- (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
- "TARGET_ALTIVEC"
- "vsumsws %0,%1,%2"
- [(set_attr "type" "veccomplex")])
-
-(define_expand "reduc_splus_<mode>"
- [(set (match_operand:VIshort 0 "register_operand" "=v")
- (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
- UNSPEC_REDUC_PLUS))]
- "TARGET_ALTIVEC"
- "
-{
- rtx vzero = gen_reg_rtx (V4SImode);
- rtx vtmp1 = gen_reg_rtx (V4SImode);
-
- emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
- emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
- emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
- DONE;
-}")
-
-(define_expand "reduc_uplus_v16qi"
- [(set (match_operand:V16QI 0 "register_operand" "=v")
- (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
- UNSPEC_REDUC_PLUS))]
- "TARGET_ALTIVEC"
- "
-{
- rtx vzero = gen_reg_rtx (V4SImode);
- rtx vtmp1 = gen_reg_rtx (V4SImode);
-
- emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
- emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
- emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
- DONE;
-}")
-
(define_insn "vec_realign_load_<mode>"
[(set (match_operand:V 0 "register_operand" "=v")
(unspec:V [(match_operand:V 1 "register_operand" "v")
@@ -2145,19 +1879,6 @@
DONE;
}")
-(define_expand "sdot_prodv8hi"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
- (match_operand:V8HI 2 "register_operand" "v")]
- UNSPEC_VMSUMSHM)))]
- "TARGET_ALTIVEC"
- "
-{
- emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2],
operands[3]));
- DONE;
-}")
-
(define_expand "widen_usum<mode>3"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
@@ -2173,36 +1894,6 @@
DONE;
}")
-(define_expand "widen_ssumv16qi3"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
- (unspec:V4SI [(match_operand:V16QI 1 "register_operand"
"v")]
- UNSPEC_VMSUMM)))]
- "TARGET_ALTIVEC"
- "
-{
- rtx vones = gen_reg_rtx (V16QImode);
-
- emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
- emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones,
operands[2]));
- DONE;
-}")
-
-(define_expand "widen_ssumv8hi3"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
- (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
- UNSPEC_VMSUMSHM)))]
- "TARGET_ALTIVEC"
- "
-{
- rtx vones = gen_reg_rtx (V8HImode);
-
- emit_insn (gen_altivec_vspltish (vones, const1_rtx));
- emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones,
operands[2]));
- DONE;
-}")
-
(define_expand "negv4sf2"
[(use (match_operand:V4SF 0 "register_operand" ""))
(use (match_operand:V4SF 1 "register_operand" ""))]
diff -uN altivec/rs6000.c vmx128/rs6000.c
--- altivec/rs6000.c 2007-08-22 09:31:46.000000000 +0100
+++ vmx128/rs6000.c 2007-08-22 09:31:21.000000000 +0100
@@ -6098,15 +6098,6 @@
static const struct builtin_description bdesc_3arg[] =
{
{ MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp",
ALTIVEC_BUILTIN_VMADDFP },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs",
ALTIVEC_BUILTIN_VMHADDSHS },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs",
ALTIVEC_BUILTIN_VMHRADDSHS },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm",
ALTIVEC_BUILTIN_VMLADDUHM},
- { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm",
ALTIVEC_BUILTIN_VMSUMUBM },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm",
ALTIVEC_BUILTIN_VMSUMMBM },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm",
ALTIVEC_BUILTIN_VMSUMUHM },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm",
ALTIVEC_BUILTIN_VMSUMSHM },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs",
ALTIVEC_BUILTIN_VMSUMUHS },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs",
ALTIVEC_BUILTIN_VMSUMSHS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp",
ALTIVEC_BUILTIN_VNMSUBFP },
{ MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf",
ALTIVEC_BUILTIN_VPERM_4SF },
{ MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si",
ALTIVEC_BUILTIN_VPERM_4SI },
@@ -6126,13 +6117,7 @@
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd",
ALTIVEC_BUILTIN_VEC_MLADD },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds",
ALTIVEC_BUILTIN_VEC_MRADDS },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum",
ALTIVEC_BUILTIN_VEC_MSUM },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm",
ALTIVEC_BUILTIN_VEC_VMSUMSHM },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm",
ALTIVEC_BUILTIN_VEC_VMSUMUHM },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm",
ALTIVEC_BUILTIN_VEC_VMSUMMBM },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm",
ALTIVEC_BUILTIN_VEC_VMSUMUBM },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums",
ALTIVEC_BUILTIN_VEC_MSUMS },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs",
ALTIVEC_BUILTIN_VEC_VMSUMSHS },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs",
ALTIVEC_BUILTIN_VEC_VMSUMUHS },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub",
ALTIVEC_BUILTIN_VEC_NMSUB },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm",
ALTIVEC_BUILTIN_VEC_PERM },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel",
ALTIVEC_BUILTIN_VEC_SEL },
@@ -6213,14 +6198,6 @@
{ MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw",
ALTIVEC_BUILTIN_VMINUW },
{ MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw",
ALTIVEC_BUILTIN_VMINSW },
{ MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp",
ALTIVEC_BUILTIN_VMINFP },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub",
ALTIVEC_BUILTIN_VMULEUB },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb",
ALTIVEC_BUILTIN_VMULESB },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh",
ALTIVEC_BUILTIN_VMULEUH },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh",
ALTIVEC_BUILTIN_VMULESH },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub",
ALTIVEC_BUILTIN_VMULOUB },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb",
ALTIVEC_BUILTIN_VMULOSB },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh",
ALTIVEC_BUILTIN_VMULOUH },
- { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh",
ALTIVEC_BUILTIN_VMULOSH },
{ MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor",
ALTIVEC_BUILTIN_VNOR },
{ MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor",
ALTIVEC_BUILTIN_VOR },
{ MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum",
ALTIVEC_BUILTIN_VPKUHUM },
@@ -6262,11 +6239,6 @@
{ MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs",
ALTIVEC_BUILTIN_VSUBSHS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws",
ALTIVEC_BUILTIN_VSUBUWS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws",
ALTIVEC_BUILTIN_VSUBSWS },
- { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs",
ALTIVEC_BUILTIN_VSUM4UBS },
- { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs",
ALTIVEC_BUILTIN_VSUM4SBS },
- { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs",
ALTIVEC_BUILTIN_VSUM4SHS },
- { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws",
ALTIVEC_BUILTIN_VSUM2SWS },
- { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws",
ALTIVEC_BUILTIN_VSUMSWS },
{ MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor",
ALTIVEC_BUILTIN_VXOR },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add",
ALTIVEC_BUILTIN_VEC_ADD },
@@ -6333,15 +6305,7 @@
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb",
ALTIVEC_BUILTIN_VEC_VMINSB },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub",
ALTIVEC_BUILTIN_VEC_VMINUB },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule",
ALTIVEC_BUILTIN_VEC_MULE },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub",
ALTIVEC_BUILTIN_VEC_VMULEUB },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb",
ALTIVEC_BUILTIN_VEC_VMULESB },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh",
ALTIVEC_BUILTIN_VEC_VMULEUH },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh",
ALTIVEC_BUILTIN_VEC_VMULESH },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo",
ALTIVEC_BUILTIN_VEC_MULO },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh",
ALTIVEC_BUILTIN_VEC_VMULOSH },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh",
ALTIVEC_BUILTIN_VEC_VMULOUH },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb",
ALTIVEC_BUILTIN_VEC_VMULOSB },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub",
ALTIVEC_BUILTIN_VEC_VMULOUB },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor",
ALTIVEC_BUILTIN_VEC_NOR },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR
},
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack",
ALTIVEC_BUILTIN_VEC_PACK },
@@ -6390,9 +6354,6 @@
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs",
ALTIVEC_BUILTIN_VEC_VSUBSBS },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs",
ALTIVEC_BUILTIN_VEC_VSUBUBS },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s",
ALTIVEC_BUILTIN_VEC_SUM4S },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs",
ALTIVEC_BUILTIN_VEC_VSUM4SHS },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs",
ALTIVEC_BUILTIN_VEC_VSUM4SBS },
- { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs",
ALTIVEC_BUILTIN_VEC_VSUM4UBS },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s",
ALTIVEC_BUILTIN_VEC_SUM2S },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums",
ALTIVEC_BUILTIN_VEC_SUMS },
{ MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor",
ALTIVEC_BUILTIN_VEC_XOR },
