28 Jul 2007 09:04:01 -0700, Ian Lance Taylor <[EMAIL PROTECTED]>: > "吴曦" <[EMAIL PROTECTED]> writes: > > > there are some questions after I read the source code today. > > 1st. if I add the instrumentation before 2nd scheduling; will gcc emit > > an insn which will be output as a ld instruction later? If this could > > happen, some ld instruction may not be instrumented... > > No, gcc won't introduce any new memory load or store instructions > after the prologue and epilogue instructions are threaded. It may ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ when are prologue and epilogue instructions threaded? (after register allocation? besides, what is the exact meaning of "prologue and epilogue instructions are threaded"? Would you mind explaining in more detail? thx :-))
> still move them around or eliminate them, though. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ emmm, I need to move/remove my instrumentation if necessary... > > > 2nd. to identify ld/st instruction (memory access op), I want to > > modify gen_rtx_SET, the method is that, if I find SRC or DST is an > > memory operand in gen_rtx_SET, then add instrumentation code before > > and after the insn to emit. Will this method work? Besides, if some > > false positives occur, how to correct them (I don't have some very > > clear idea.) > > Modifying gen_rtx_SET is probably not the right way to go. That is ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Then, what about modifying machine description file? Add define_expand for the define_insn which will output ld/st instruction (this define_expand can insert instrumentation insns. Of course, I need to identify the operands to the define_expand contains a memory operand and a reg operand.) > used in many places throughout the RTL passes. Not all of those > places are going to be able to cope with the new instructions you want > to add. > > Ian > Thanks for your hints again :-)
