Zdenek Dvorak wrote:
...
The number of parallel "computations" in loop.
The estimated latency of the critical path of loop.
The estimated cycle length of loop body.
The max. dependence height of computations.
The max. height of memory dependencies of computations.
The max. height of control dependencies of computations.
The average dependence height of computations.
The min. memory-to-memory loop-carried dependence.
The number of memory-to-memory dependencies.
This is a bit more difficult; I guess you could persuade scheduler to
give you this information, but I have no idea how exactly. See
modulo-sched.c, it considers similar kind of information.
Stefan,
You can get a DDG for an acyclic graph (which one iteration of the loop
is :) from sched-deps.c. From that DDG it should not be difficult to
compute properties you want. If you want to get interloop properties,
then take a look at ddg.c - modulo-sched.c uses it to build interloop
dependencies.
--
Maxim
