Again with attachment and CC to the Mailing List. Sorry for missing this.
Regards,
Markus
---
Hello,
thanks for your instructions. Indeed you were right. I mixed up some files.
Again an excerpt of the output-files:
---snip--- // expand
(insn 45 47 46 1 (set (subreg:SI (reg:DI 92 [ D.1212 ]) 4)
(reg:SI 93 [ D.1211 ])) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:SI 93 [ D.1211 ])
(nil)))
---snap---
---snip--- // lreg
(insn 45 47 46 0 (set (subreg:SI (reg:DI 92 [ D.1212 ]) 4)
(reg:SI 93 [ D.1211 ])) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:SI 93 [ D.1211 ])
(expr_list:REG_NO_CONFLICT (reg:SI 93 [ D.1211 ])
(nil))))
---snap---
---snip--- // greg
;; Function main (main)
Spilling for insn 45.
---snap---
Aditionally, you can find the three files in the attachment. It would be
really nice of you if you could have a look at it. Maybe you can get a
clue what's going wrong.
Regards,
Markus Franke
Jim Wilson wrote:
> Markus Franke wrote:
>
>> That means the compiler has to reload the pseudo registers 92 and 93 for
>> this instruction, right?
>
>
> First we do register allocation. Then, after register allocation, if
> the chosen hard registers don't match the constraints, then we use
> reload to fix it.
>
>> The relevant data for instruction 45 in .greg looks like that:
>
>
> Insn 45 in the greg dump looks nothing like the insn 45 in the expand
> dump, which means you are looking at the wrong insn here. But it was
> insn 45 in the original mail. Did you change the testcase perhaps? Or
> use different optimization options?
>
> The info we are looking for should look something like this
> Reloads for insn # 13
> Reload 0: reload_out (SI) = (reg:SI 97)
> R1_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
> reload_out_reg: (reg:SI 97)
> reload_reg_rtx: (reg:SI 1 %r1)
>
>> ;; Register 92 in 9.
>> ;; Register 93 in 10.
>
>
> This tells us that pseudo 92 was allocated to hard reg 9, and pseudo 93
> was allocated to hard reg 10. I didn't see reg class preferencing info
> for these regs, but maybe it is in one of the other dump files.
>
> The earlier message has rtl claiming that pseudo 92 got allocated to
> register 1 (r1). I seem to be getting inconsistent information here.
--
Nichts ist so praktisch wie eine gute Theorie!
;; Function main (main)
;; Generating RTL for tree basic block 0
;;
;; Full RTL generated for this function:
;;
(note 2 0 6 NOTE_INSN_DELETED)
;; Start of basic block 0, registers live: (nil)
(note 6 2 3 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(note 3 6 180 0 NOTE_INSN_FUNCTION_BEG)
(insn 180 3 4 0 (set (reg:SI 139)
(reg/f:SI 29 r29)) -1 (nil)
(nil))
(note 4 180 5 0 NOTE_INSN_DELETED)
(call_insn 5 4 7 0 (parallel [
(call (mem:QI (symbol_ref:SI ("__main") [flags 0x41]) [0 S1 A8])
(const_int 0 [0x0]))
(clobber (reg:SI 31 r31))
]) -1 (nil)
(expr_list:REG_EH_REGION (const_int 0 [0x0])
(nil))
(nil))
;; End of basic block 0, registers live:
(nil)
;; Start of basic block 1, registers live: (nil)
(note 7 5 8 1 [bb 1] NOTE_INSN_BASIC_BLOCK)
(insn 8 7 9 1 (set (reg:SI 108)
(reg/f:SI 29 r29)) -1 (nil)
(nil))
(insn 9 8 11 1 (set (reg:SI 70 [ saved_stack3 ])
(reg:SI 108)) -1 (nil)
(nil))
(insn 11 9 12 1 (set (reg/f:SI 109)
(symbol_ref:SI ("c") [flags 0x2] <var_decl 0x3adb3108 c>)) -1 (nil)
(nil))
(insn 12 11 13 1 (set (reg:HI 106 [ c0 ])
(mem/c/i:HI (reg/f:SI 109) [0 c+0 S2 A16])) -1 (nil)
(nil))
(insn 13 12 14 1 (set (reg:SI 105 [ D.1199 ])
(sign_extend:SI (reg:HI 106 [ c0 ]))) -1 (nil)
(nil))
(insn 14 13 15 1 (set (reg:SI 104 [ D.1200 ])
(plus:SI (reg:SI 105 [ D.1199 ])
(const_int -1 [0xffffffff]))) -1 (nil)
(nil))
(insn 15 14 16 1 (set (reg:SI 103 [ D.1201 ])
(reg:SI 104 [ D.1200 ])) -1 (nil)
(nil))
(insn 16 15 19 1 (set (reg:SI 102 [ D.1202 ])
(sign_extend:SI (reg:HI 106 [ c0 ]))) -1 (nil)
(nil))
(insn 19 16 17 1 (clobber (reg:DI 101 [ D.1203 ])) -1 (nil)
(insn_list:REG_LIBCALL 18 (nil)))
(insn 17 19 18 1 (set (subreg:SI (reg:DI 101 [ D.1203 ]) 4)
(reg:SI 102 [ D.1202 ])) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:SI 102 [ D.1202 ])
(nil)))
(insn 18 17 22 1 (set (subreg:SI (reg:DI 101 [ D.1203 ]) 0)
(const_int 0 [0x0])) -1 (nil)
(insn_list:REG_RETVAL 19 (expr_list:REG_NO_CONFLICT (reg:SI 102 [ D.1202 ])
(nil))))
(insn 22 18 20 1 (clobber (reg:DI 110)) -1 (nil)
(insn_list:REG_LIBCALL 21 (nil)))
(insn 20 22 21 1 (set (subreg:SI (reg:DI 110) 0)
(and:SI (subreg:SI (reg:DI 101 [ D.1203 ]) 0)
(const_int 15 [0xf]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 101 [ D.1203 ])
(nil)))
(insn 21 20 25 1 (set (subreg:SI (reg:DI 110) 4)
(and:SI (subreg:SI (reg:DI 101 [ D.1203 ]) 4)
(const_int -1 [0xffffffff]))) -1 (nil)
(insn_list:REG_RETVAL 22 (expr_list:REG_NO_CONFLICT (reg:DI 101 [ D.1203 ])
(nil))))
(insn 25 21 23 1 (clobber (reg:DI 101 [ D.1203 ])) -1 (nil)
(nil))
(insn 23 25 24 1 (set (subreg:SI (reg:DI 101 [ D.1203 ]) 0)
(subreg:SI (reg:DI 110) 0)) -1 (nil)
(nil))
(insn 24 23 26 1 (set (subreg:SI (reg:DI 101 [ D.1203 ]) 4)
(subreg:SI (reg:DI 110) 4)) -1 (nil)
(nil))
(insn 26 24 30 1 (set (reg:SI 111)
(lshiftrt:SI (subreg:SI (reg:DI 101 [ D.1203 ]) 4)
(const_int 27 [0x1b]))) -1 (nil)
(nil))
(insn 30 26 27 1 (clobber (reg:DI 100 [ D.1204 ])) -1 (nil)
(insn_list:REG_LIBCALL 29 (nil)))
(insn 27 30 28 1 (set (subreg:SI (reg:DI 100 [ D.1204 ]) 0)
(ashift:SI (subreg:SI (reg:DI 101 [ D.1203 ]) 0)
(const_int 5 [0x5]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 101 [ D.1203 ])
(nil)))
(insn 28 27 29 1 (set (subreg:SI (reg:DI 100 [ D.1204 ]) 0)
(ior:SI (subreg:SI (reg:DI 100 [ D.1204 ]) 0)
(reg:SI 111))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 101 [ D.1203 ])
(nil)))
(insn 29 28 33 1 (set (subreg:SI (reg:DI 100 [ D.1204 ]) 4)
(ashift:SI (subreg:SI (reg:DI 101 [ D.1203 ]) 4)
(const_int 5 [0x5]))) -1 (nil)
(insn_list:REG_RETVAL 30 (expr_list:REG_NO_CONFLICT (reg:DI 101 [ D.1203 ])
(nil))))
(insn 33 29 31 1 (clobber (reg:DI 112)) -1 (nil)
(insn_list:REG_LIBCALL 32 (nil)))
(insn 31 33 32 1 (set (subreg:SI (reg:DI 112) 0)
(and:SI (subreg:SI (reg:DI 100 [ D.1204 ]) 0)
(const_int 15 [0xf]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 100 [ D.1204 ])
(nil)))
(insn 32 31 36 1 (set (subreg:SI (reg:DI 112) 4)
(and:SI (subreg:SI (reg:DI 100 [ D.1204 ]) 4)
(const_int -1 [0xffffffff]))) -1 (nil)
(insn_list:REG_RETVAL 33 (expr_list:REG_NO_CONFLICT (reg:DI 100 [ D.1204 ])
(nil))))
(insn 36 32 34 1 (clobber (reg:DI 100 [ D.1204 ])) -1 (nil)
(nil))
(insn 34 36 35 1 (set (subreg:SI (reg:DI 100 [ D.1204 ]) 0)
(subreg:SI (reg:DI 112) 0)) -1 (nil)
(nil))
(insn 35 34 37 1 (set (subreg:SI (reg:DI 100 [ D.1204 ]) 4)
(subreg:SI (reg:DI 112) 4)) -1 (nil)
(nil))
(insn 37 35 38 1 (set (reg:SI 99 [ D.1205 ])
(sign_extend:SI (reg:HI 106 [ c0 ]))) -1 (nil)
(nil))
(insn 38 37 39 1 (set (reg:SI 98 [ D.1206 ])
(ashift:SI (reg:SI 99 [ D.1205 ])
(const_int 2 [0x2]))) -1 (nil)
(nil))
(insn 39 38 40 1 (set (reg/f:SI 113)
(symbol_ref:SI ("b") [flags 0x2] <var_decl 0x3adb30b0 b>)) -1 (nil)
(nil))
(insn 40 39 41 1 (set (reg:HI 97 [ b1 ])
(mem/c/i:HI (reg/f:SI 113) [0 b+0 S2 A16])) -1 (nil)
(nil))
(insn 41 40 42 1 (set (reg:SI 96 [ D.1208 ])
(sign_extend:SI (reg:HI 97 [ b1 ]))) -1 (nil)
(nil))
(insn 42 41 43 1 (set (reg:SI 95 [ D.1209 ])
(plus:SI (reg:SI 96 [ D.1208 ])
(const_int -1 [0xffffffff]))) -1 (nil)
(nil))
(insn 43 42 44 1 (set (reg:SI 94 [ D.1210 ])
(reg:SI 95 [ D.1209 ])) -1 (nil)
(nil))
(insn 44 43 47 1 (set (reg:SI 93 [ D.1211 ])
(sign_extend:SI (reg:HI 106 [ c0 ]))) -1 (nil)
(nil))
(insn 47 44 45 1 (clobber (reg:DI 92 [ D.1212 ])) -1 (nil)
(insn_list:REG_LIBCALL 46 (nil)))
(insn 45 47 46 1 (set (subreg:SI (reg:DI 92 [ D.1212 ]) 4)
(reg:SI 93 [ D.1211 ])) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:SI 93 [ D.1211 ])
(nil)))
(insn 46 45 50 1 (set (subreg:SI (reg:DI 92 [ D.1212 ]) 0)
(const_int 0 [0x0])) -1 (nil)
(insn_list:REG_RETVAL 47 (expr_list:REG_NO_CONFLICT (reg:SI 93 [ D.1211 ])
(nil))))
(insn 50 46 48 1 (clobber (reg:DI 114)) -1 (nil)
(insn_list:REG_LIBCALL 49 (nil)))
(insn 48 50 49 1 (set (subreg:SI (reg:DI 114) 0)
(and:SI (subreg:SI (reg:DI 92 [ D.1212 ]) 0)
(const_int 15 [0xf]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 92 [ D.1212 ])
(nil)))
(insn 49 48 53 1 (set (subreg:SI (reg:DI 114) 4)
(and:SI (subreg:SI (reg:DI 92 [ D.1212 ]) 4)
(const_int -1 [0xffffffff]))) -1 (nil)
(insn_list:REG_RETVAL 50 (expr_list:REG_NO_CONFLICT (reg:DI 92 [ D.1212 ])
(nil))))
(insn 53 49 51 1 (clobber (reg:DI 92 [ D.1212 ])) -1 (nil)
(nil))
(insn 51 53 52 1 (set (subreg:SI (reg:DI 92 [ D.1212 ]) 0)
(subreg:SI (reg:DI 114) 0)) -1 (nil)
(nil))
(insn 52 51 54 1 (set (subreg:SI (reg:DI 92 [ D.1212 ]) 4)
(subreg:SI (reg:DI 114) 4)) -1 (nil)
(nil))
(insn 54 52 57 1 (set (reg:SI 91 [ D.1213 ])
(sign_extend:SI (reg:HI 97 [ b1 ]))) -1 (nil)
(nil))
(insn 57 54 55 1 (clobber (reg:DI 90 [ D.1214 ])) -1 (nil)
(insn_list:REG_LIBCALL 56 (nil)))
(insn 55 57 56 1 (set (subreg:SI (reg:DI 90 [ D.1214 ]) 4)
(reg:SI 91 [ D.1213 ])) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:SI 91 [ D.1213 ])
(nil)))
(insn 56 55 60 1 (set (subreg:SI (reg:DI 90 [ D.1214 ]) 0)
(const_int 0 [0x0])) -1 (nil)
(insn_list:REG_RETVAL 57 (expr_list:REG_NO_CONFLICT (reg:SI 91 [ D.1213 ])
(nil))))
(insn 60 56 58 1 (clobber (reg:DI 115)) -1 (nil)
(insn_list:REG_LIBCALL 59 (nil)))
(insn 58 60 59 1 (set (subreg:SI (reg:DI 115) 0)
(and:SI (subreg:SI (reg:DI 90 [ D.1214 ]) 0)
(const_int 15 [0xf]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 90 [ D.1214 ])
(nil)))
(insn 59 58 63 1 (set (subreg:SI (reg:DI 115) 4)
(and:SI (subreg:SI (reg:DI 90 [ D.1214 ]) 4)
(const_int -1 [0xffffffff]))) -1 (nil)
(insn_list:REG_RETVAL 60 (expr_list:REG_NO_CONFLICT (reg:DI 90 [ D.1214 ])
(nil))))
(insn 63 59 61 1 (clobber (reg:DI 90 [ D.1214 ])) -1 (nil)
(nil))
(insn 61 63 62 1 (set (subreg:SI (reg:DI 90 [ D.1214 ]) 0)
(subreg:SI (reg:DI 115) 0)) -1 (nil)
(nil))
(insn 62 61 64 1 (set (subreg:SI (reg:DI 90 [ D.1214 ]) 4)
(subreg:SI (reg:DI 115) 4)) -1 (nil)
(nil))
(insn 64 62 65 1 (set (reg:SI 116)
(plus:SI (reg/f:SI 66 virtual-stack-vars)
(const_int -16 [0xfffffff0]))) -1 (nil)
(nil))
(insn 65 64 66 1 (set (reg/f:SI 29 r29)
(plus:SI (reg/f:SI 29 r29)
(const_int -24 [0xffffffe8]))) -1 (nil)
(insn_list:REG_LIBCALL 74 (nil)))
(insn 66 65 67 1 (set (mem:SI (reg/f:SI 68 virtual-outgoing-args) [0 S4 A32])
(reg:SI 116)) -1 (nil)
(nil))
(insn 67 66 68 1 (set (mem:SI (plus:SI (reg/f:SI 68 virtual-outgoing-args)
(const_int 8 [0x8])) [0 S4 A32])
(subreg:SI (reg:DI 92 [ D.1212 ]) 0)) -1 (nil)
(nil))
(insn 68 67 69 1 (set (mem:SI (plus:SI (reg/f:SI 68 virtual-outgoing-args)
(const_int 12 [0xc])) [0 S4 A32])
(subreg:SI (reg:DI 92 [ D.1212 ]) 4)) -1 (nil)
(nil))
(insn 69 68 70 1 (set (mem:SI (plus:SI (reg/f:SI 68 virtual-outgoing-args)
(const_int 16 [0x10])) [0 S4 A32])
(subreg:SI (reg:DI 90 [ D.1214 ]) 0)) -1 (nil)
(nil))
(insn 70 69 71 1 (set (mem:SI (plus:SI (reg/f:SI 68 virtual-outgoing-args)
(const_int 20 [0x14])) [0 S4 A32])
(subreg:SI (reg:DI 90 [ D.1214 ]) 4)) -1 (nil)
(nil))
(call_insn 71 70 72 1 (parallel [
(call (mem:QI (symbol_ref:SI ("__muldi3") [flags 0x41]) [0 S1 A8])
(const_int 24 [0x18]))
(clobber (reg:SI 31 r31))
]) -1 (nil)
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))
(nil))
(insn 72 71 75 1 (set (reg/f:SI 29 r29)
(plus:SI (reg/f:SI 29 r29)
(const_int 24 [0x18]))) -1 (nil)
(nil))
(insn 75 72 73 1 (clobber (reg:DI 117)) -1 (nil)
(nil))
(insn 73 75 74 1 (set (subreg:SI (reg:DI 117) 0)
(mem/c/i:SI (plus:SI (reg/f:SI 66 virtual-stack-vars)
(const_int -16 [0xfffffff0])) [0 S4 A64])) -1 (nil)
(nil))
(insn 74 73 78 1 (set (subreg:SI (reg:DI 117) 4)
(mem/c/i:SI (plus:SI (reg/f:SI 66 virtual-stack-vars)
(const_int -12 [0xfffffff4])) [0 S4 A32])) -1 (nil)
(insn_list:REG_RETVAL 65 (nil)))
(insn 78 74 76 1 (clobber (reg:DI 89 [ D.1215 ])) -1 (nil)
(insn_list:REG_LIBCALL 77 (nil)))
(insn 76 78 77 1 (set (subreg:SI (reg:DI 89 [ D.1215 ]) 0)
(and:SI (subreg:SI (reg:DI 117) 0)
(const_int 15 [0xf]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 117)
(nil)))
(insn 77 76 79 1 (set (subreg:SI (reg:DI 89 [ D.1215 ]) 4)
(and:SI (subreg:SI (reg:DI 117) 4)
(const_int -1 [0xffffffff]))) -1 (nil)
(insn_list:REG_RETVAL 78 (expr_list:REG_NO_CONFLICT (reg:DI 117)
(nil))))
(insn 79 77 83 1 (set (reg:SI 118)
(lshiftrt:SI (subreg:SI (reg:DI 89 [ D.1215 ]) 4)
(const_int 27 [0x1b]))) -1 (nil)
(nil))
(insn 83 79 80 1 (clobber (reg:DI 88 [ D.1216 ])) -1 (nil)
(insn_list:REG_LIBCALL 82 (nil)))
(insn 80 83 81 1 (set (subreg:SI (reg:DI 88 [ D.1216 ]) 0)
(ashift:SI (subreg:SI (reg:DI 89 [ D.1215 ]) 0)
(const_int 5 [0x5]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 89 [ D.1215 ])
(nil)))
(insn 81 80 82 1 (set (subreg:SI (reg:DI 88 [ D.1216 ]) 0)
(ior:SI (subreg:SI (reg:DI 88 [ D.1216 ]) 0)
(reg:SI 118))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 89 [ D.1215 ])
(nil)))
(insn 82 81 86 1 (set (subreg:SI (reg:DI 88 [ D.1216 ]) 4)
(ashift:SI (subreg:SI (reg:DI 89 [ D.1215 ]) 4)
(const_int 5 [0x5]))) -1 (nil)
(insn_list:REG_RETVAL 83 (expr_list:REG_NO_CONFLICT (reg:DI 89 [ D.1215 ])
(nil))))
(insn 86 82 84 1 (clobber (reg:DI 119)) -1 (nil)
(insn_list:REG_LIBCALL 85 (nil)))
(insn 84 86 85 1 (set (subreg:SI (reg:DI 119) 0)
(and:SI (subreg:SI (reg:DI 88 [ D.1216 ]) 0)
(const_int 15 [0xf]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 88 [ D.1216 ])
(nil)))
(insn 85 84 89 1 (set (subreg:SI (reg:DI 119) 4)
(and:SI (subreg:SI (reg:DI 88 [ D.1216 ]) 4)
(const_int -1 [0xffffffff]))) -1 (nil)
(insn_list:REG_RETVAL 86 (expr_list:REG_NO_CONFLICT (reg:DI 88 [ D.1216 ])
(nil))))
(insn 89 85 87 1 (clobber (reg:DI 88 [ D.1216 ])) -1 (nil)
(nil))
(insn 87 89 88 1 (set (subreg:SI (reg:DI 88 [ D.1216 ]) 0)
(subreg:SI (reg:DI 119) 0)) -1 (nil)
(nil))
(insn 88 87 90 1 (set (subreg:SI (reg:DI 88 [ D.1216 ]) 4)
(subreg:SI (reg:DI 119) 4)) -1 (nil)
(nil))
(insn 90 88 91 1 (set (reg:SI 87 [ D.1217 ])
(sign_extend:SI (reg:HI 106 [ c0 ]))) -1 (nil)
(nil))
(insn 91 90 92 1 (set (reg:SI 86 [ D.1218 ])
(sign_extend:SI (reg:HI 97 [ b1 ]))) -1 (nil)
(nil))
(insn 92 91 93 1 (parallel [
(set (reg:SI 85 [ D.1219 ])
(mult:SI (reg:SI 87 [ D.1217 ])
(reg:SI 86 [ D.1218 ])))
(clobber (scratch:SF))
(clobber (scratch:SF))
]) -1 (nil)
(nil))
(insn 93 92 94 1 (set (reg:SI 84 [ D.1220 ])
(ashift:SI (reg:SI 85 [ D.1219 ])
(const_int 2 [0x2]))) -1 (nil)
(nil))
(insn 94 93 97 1 (set (reg:SI 83 [ D.1221 ])
(sign_extend:SI (reg:HI 106 [ c0 ]))) -1 (nil)
(nil))
(insn 97 94 95 1 (clobber (reg:DI 82 [ D.1222 ])) -1 (nil)
(insn_list:REG_LIBCALL 96 (nil)))
(insn 95 97 96 1 (set (subreg:SI (reg:DI 82 [ D.1222 ]) 4)
(reg:SI 83 [ D.1221 ])) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:SI 83 [ D.1221 ])
(nil)))
(insn 96 95 100 1 (set (subreg:SI (reg:DI 82 [ D.1222 ]) 0)
(const_int 0 [0x0])) -1 (nil)
(insn_list:REG_RETVAL 97 (expr_list:REG_NO_CONFLICT (reg:SI 83 [ D.1221 ])
(nil))))
(insn 100 96 98 1 (clobber (reg:DI 120)) -1 (nil)
(insn_list:REG_LIBCALL 99 (nil)))
(insn 98 100 99 1 (set (subreg:SI (reg:DI 120) 0)
(and:SI (subreg:SI (reg:DI 82 [ D.1222 ]) 0)
(const_int 15 [0xf]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 82 [ D.1222 ])
(nil)))
(insn 99 98 103 1 (set (subreg:SI (reg:DI 120) 4)
(and:SI (subreg:SI (reg:DI 82 [ D.1222 ]) 4)
(const_int -1 [0xffffffff]))) -1 (nil)
(insn_list:REG_RETVAL 100 (expr_list:REG_NO_CONFLICT (reg:DI 82 [ D.1222 ])
(nil))))
(insn 103 99 101 1 (clobber (reg:DI 82 [ D.1222 ])) -1 (nil)
(nil))
(insn 101 103 102 1 (set (subreg:SI (reg:DI 82 [ D.1222 ]) 0)
(subreg:SI (reg:DI 120) 0)) -1 (nil)
(nil))
(insn 102 101 104 1 (set (subreg:SI (reg:DI 82 [ D.1222 ]) 4)
(subreg:SI (reg:DI 120) 4)) -1 (nil)
(nil))
(insn 104 102 107 1 (set (reg:SI 81 [ D.1223 ])
(sign_extend:SI (reg:HI 97 [ b1 ]))) -1 (nil)
(nil))
(insn 107 104 105 1 (clobber (reg:DI 80 [ D.1224 ])) -1 (nil)
(insn_list:REG_LIBCALL 106 (nil)))
(insn 105 107 106 1 (set (subreg:SI (reg:DI 80 [ D.1224 ]) 4)
(reg:SI 81 [ D.1223 ])) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:SI 81 [ D.1223 ])
(nil)))
(insn 106 105 110 1 (set (subreg:SI (reg:DI 80 [ D.1224 ]) 0)
(const_int 0 [0x0])) -1 (nil)
(insn_list:REG_RETVAL 107 (expr_list:REG_NO_CONFLICT (reg:SI 81 [ D.1223 ])
(nil))))
(insn 110 106 108 1 (clobber (reg:DI 121)) -1 (nil)
(insn_list:REG_LIBCALL 109 (nil)))
(insn 108 110 109 1 (set (subreg:SI (reg:DI 121) 0)
(and:SI (subreg:SI (reg:DI 80 [ D.1224 ]) 0)
(const_int 15 [0xf]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 80 [ D.1224 ])
(nil)))
(insn 109 108 113 1 (set (subreg:SI (reg:DI 121) 4)
(and:SI (subreg:SI (reg:DI 80 [ D.1224 ]) 4)
(const_int -1 [0xffffffff]))) -1 (nil)
(insn_list:REG_RETVAL 110 (expr_list:REG_NO_CONFLICT (reg:DI 80 [ D.1224 ])
(nil))))
(insn 113 109 111 1 (clobber (reg:DI 80 [ D.1224 ])) -1 (nil)
(nil))
(insn 111 113 112 1 (set (subreg:SI (reg:DI 80 [ D.1224 ]) 0)
(subreg:SI (reg:DI 121) 0)) -1 (nil)
(nil))
(insn 112 111 114 1 (set (subreg:SI (reg:DI 80 [ D.1224 ]) 4)
(subreg:SI (reg:DI 121) 4)) -1 (nil)
(nil))
(insn 114 112 115 1 (set (reg:SI 122)
(plus:SI (reg/f:SI 66 virtual-stack-vars)
(const_int -16 [0xfffffff0]))) -1 (nil)
(nil))
(insn 115 114 116 1 (set (reg/f:SI 29 r29)
(plus:SI (reg/f:SI 29 r29)
(const_int -24 [0xffffffe8]))) -1 (nil)
(insn_list:REG_LIBCALL 124 (nil)))
(insn 116 115 117 1 (set (mem:SI (reg/f:SI 68 virtual-outgoing-args) [0 S4 A32])
(reg:SI 122)) -1 (nil)
(nil))
(insn 117 116 118 1 (set (mem:SI (plus:SI (reg/f:SI 68 virtual-outgoing-args)
(const_int 8 [0x8])) [0 S4 A32])
(subreg:SI (reg:DI 82 [ D.1222 ]) 0)) -1 (nil)
(nil))
(insn 118 117 119 1 (set (mem:SI (plus:SI (reg/f:SI 68 virtual-outgoing-args)
(const_int 12 [0xc])) [0 S4 A32])
(subreg:SI (reg:DI 82 [ D.1222 ]) 4)) -1 (nil)
(nil))
(insn 119 118 120 1 (set (mem:SI (plus:SI (reg/f:SI 68 virtual-outgoing-args)
(const_int 16 [0x10])) [0 S4 A32])
(subreg:SI (reg:DI 80 [ D.1224 ]) 0)) -1 (nil)
(nil))
(insn 120 119 121 1 (set (mem:SI (plus:SI (reg/f:SI 68 virtual-outgoing-args)
(const_int 20 [0x14])) [0 S4 A32])
(subreg:SI (reg:DI 80 [ D.1224 ]) 4)) -1 (nil)
(nil))
(call_insn 121 120 122 1 (parallel [
(call (mem:QI (symbol_ref:SI ("__muldi3") [flags 0x41]) [0 S1 A8])
(const_int 24 [0x18]))
(clobber (reg:SI 31 r31))
]) -1 (nil)
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))
(nil))
(insn 122 121 125 1 (set (reg/f:SI 29 r29)
(plus:SI (reg/f:SI 29 r29)
(const_int 24 [0x18]))) -1 (nil)
(nil))
(insn 125 122 123 1 (clobber (reg:DI 123)) -1 (nil)
(nil))
(insn 123 125 124 1 (set (subreg:SI (reg:DI 123) 0)
(mem/c/i:SI (plus:SI (reg/f:SI 66 virtual-stack-vars)
(const_int -16 [0xfffffff0])) [0 S4 A64])) -1 (nil)
(nil))
(insn 124 123 128 1 (set (subreg:SI (reg:DI 123) 4)
(mem/c/i:SI (plus:SI (reg/f:SI 66 virtual-stack-vars)
(const_int -12 [0xfffffff4])) [0 S4 A32])) -1 (nil)
(insn_list:REG_RETVAL 115 (nil)))
(insn 128 124 126 1 (clobber (reg:DI 79 [ D.1225 ])) -1 (nil)
(insn_list:REG_LIBCALL 127 (nil)))
(insn 126 128 127 1 (set (subreg:SI (reg:DI 79 [ D.1225 ]) 0)
(and:SI (subreg:SI (reg:DI 123) 0)
(const_int 15 [0xf]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 123)
(nil)))
(insn 127 126 129 1 (set (subreg:SI (reg:DI 79 [ D.1225 ]) 4)
(and:SI (subreg:SI (reg:DI 123) 4)
(const_int -1 [0xffffffff]))) -1 (nil)
(insn_list:REG_RETVAL 128 (expr_list:REG_NO_CONFLICT (reg:DI 123)
(nil))))
(insn 129 127 133 1 (set (reg:SI 124)
(lshiftrt:SI (subreg:SI (reg:DI 79 [ D.1225 ]) 4)
(const_int 27 [0x1b]))) -1 (nil)
(nil))
(insn 133 129 130 1 (clobber (reg:DI 78 [ D.1226 ])) -1 (nil)
(insn_list:REG_LIBCALL 132 (nil)))
(insn 130 133 131 1 (set (subreg:SI (reg:DI 78 [ D.1226 ]) 0)
(ashift:SI (subreg:SI (reg:DI 79 [ D.1225 ]) 0)
(const_int 5 [0x5]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 79 [ D.1225 ])
(nil)))
(insn 131 130 132 1 (set (subreg:SI (reg:DI 78 [ D.1226 ]) 0)
(ior:SI (subreg:SI (reg:DI 78 [ D.1226 ]) 0)
(reg:SI 124))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 79 [ D.1225 ])
(nil)))
(insn 132 131 136 1 (set (subreg:SI (reg:DI 78 [ D.1226 ]) 4)
(ashift:SI (subreg:SI (reg:DI 79 [ D.1225 ]) 4)
(const_int 5 [0x5]))) -1 (nil)
(insn_list:REG_RETVAL 133 (expr_list:REG_NO_CONFLICT (reg:DI 79 [ D.1225 ])
(nil))))
(insn 136 132 134 1 (clobber (reg:DI 125)) -1 (nil)
(insn_list:REG_LIBCALL 135 (nil)))
(insn 134 136 135 1 (set (subreg:SI (reg:DI 125) 0)
(and:SI (subreg:SI (reg:DI 78 [ D.1226 ]) 0)
(const_int 15 [0xf]))) -1 (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 78 [ D.1226 ])
(nil)))
(insn 135 134 139 1 (set (subreg:SI (reg:DI 125) 4)
(and:SI (subreg:SI (reg:DI 78 [ D.1226 ]) 4)
(const_int -1 [0xffffffff]))) -1 (nil)
(insn_list:REG_RETVAL 136 (expr_list:REG_NO_CONFLICT (reg:DI 78 [ D.1226 ])
(nil))))
(insn 139 135 137 1 (clobber (reg:DI 78 [ D.1226 ])) -1 (nil)
(nil))
(insn 137 139 138 1 (set (subreg:SI (reg:DI 78 [ D.1226 ]) 0)
(subreg:SI (reg:DI 125) 0)) -1 (nil)
(nil))
(insn 138 137 140 1 (set (subreg:SI (reg:DI 78 [ D.1226 ]) 4)
(subreg:SI (reg:DI 125) 4)) -1 (nil)
(nil))
(insn 140 138 141 1 (set (reg:SI 77 [ D.1227 ])
(sign_extend:SI (reg:HI 106 [ c0 ]))) -1 (nil)
(nil))
(insn 141 140 142 1 (set (reg:SI 76 [ D.1228 ])
(sign_extend:SI (reg:HI 97 [ b1 ]))) -1 (nil)
(nil))
(insn 142 141 143 1 (parallel [
(set (reg:SI 75 [ D.1229 ])
(mult:SI (reg:SI 77 [ D.1227 ])
(reg:SI 76 [ D.1228 ])))
(clobber (scratch:SF))
(clobber (scratch:SF))
]) -1 (nil)
(nil))
(insn 143 142 144 1 (set (reg:SI 74 [ D.1230 ])
(ashift:SI (reg:SI 75 [ D.1229 ])
(const_int 2 [0x2]))) -1 (nil)
(nil))
(insn 144 143 145 1 (set (reg:SI 126)
(plus:SI (reg:SI 74 [ D.1230 ])
(const_int 7 [0x7]))) -1 (nil)
(nil))
(insn 145 144 146 1 (set (reg:SI 127)
(plus:SI (reg:SI 126)
(const_int 7 [0x7]))) -1 (nil)
(nil))
(insn 146 145 147 1 (set (reg:SI 128)
(lshiftrt:SI (reg:SI 127)
(const_int 3 [0x3]))) -1 (nil)
(expr_list:REG_EQUAL (udiv:SI (reg:SI 127)
(const_int 8 [0x8]))
(nil)))
(insn 147 146 148 1 (set (reg:SI 129)
(ashift:SI (reg:SI 128)
(const_int 3 [0x3]))) -1 (nil)
(nil))
(insn 148 147 149 1 (set (reg/f:SI 29 r29)
(minus:SI (reg/f:SI 29 r29)
(reg:SI 129))) -1 (nil)
(nil))
(insn 149 148 150 1 (set (reg/f:SI 73 [ D.1232 ])
(reg/f:SI 67 virtual-stack-dynamic)) -1 (nil)
(nil))
(insn 150 149 151 1 (set (reg:SI 130)
(plus:SI (reg/f:SI 73 [ D.1232 ])
(const_int 7 [0x7]))) -1 (nil)
(nil))
(insn 151 150 152 1 (set (reg:SI 131)
(lshiftrt:SI (reg:SI 130)
(const_int 3 [0x3]))) -1 (nil)
(expr_list:REG_EQUAL (udiv:SI (reg:SI 130)
(const_int 8 [0x8]))
(nil)))
(insn 152 151 153 1 (set (reg:SI 132)
(ashift:SI (reg:SI 131)
(const_int 3 [0x3]))) -1 (nil)
(nil))
(insn 153 152 154 1 (set (reg/f:SI 73 [ D.1232 ])
(reg:SI 132)) -1 (nil)
(nil))
(insn 154 153 156 1 (set (mem/f/c/i:SI (plus:SI (reg/f:SI 66 virtual-stack-vars)
(const_int -4 [0xfffffffc])) [0 a2+0 S4 A32])
(reg/f:SI 73 [ D.1232 ])) -1 (nil)
(nil))
(insn 156 154 157 1 (set (reg:SI 72 [ D.1233 ])
(lshiftrt:SI (reg:SI 98 [ D.1206 ])
(const_int 2 [0x2]))) -1 (nil)
(expr_list:REG_EQUAL (udiv:SI (reg:SI 98 [ D.1206 ])
(const_int 4 [0x4]))
(nil)))
(insn 157 156 158 1 (set (reg/f:SI 133)
(mem/f/c/i:SI (plus:SI (reg/f:SI 66 virtual-stack-vars)
(const_int -4 [0xfffffffc])) [0 a2+0 S4 A32])) -1 (nil)
(nil))
(insn 158 157 159 1 (set (reg:SI 134)
(ashift:SI (reg:SI 72 [ D.1233 ])
(const_int 2 [0x2]))) -1 (nil)
(nil))
(insn 159 158 160 1 (set (reg:SI 135)
(plus:SI (reg:SI 134)
(reg/f:SI 133))) -1 (nil)
(nil))
(insn 160 159 161 1 (set (reg/f:SI 136)
(plus:SI (reg:SI 135)
(const_int 4 [0x4]))) -1 (nil)
(nil))
(insn 161 160 162 1 (set (reg:SI 137)
(const_int 5 [0x5])) -1 (nil)
(nil))
(insn 162 161 164 1 (set (mem/s/j:SI (reg/f:SI 136) [0 S4 A32])
(reg:SI 137)) -1 (nil)
(nil))
(insn 164 162 165 1 (set (reg:SI 71 [ D.1234 ])
(const_int 0 [0x0])) -1 (nil)
(nil))
(insn 165 164 166 1 (clobber (mem:BLK (scratch) [0 A8])) -1 (nil)
(nil))
(insn 166 165 167 1 (clobber (mem:BLK (reg/f:SI 29 r29) [0 A8])) -1 (nil)
(nil))
(insn 167 166 168 1 (set (reg/f:SI 29 r29)
(reg:SI 70 [ saved_stack3 ])) -1 (nil)
(nil))
(insn 168 167 169 1 (set (reg:SI 107 [ <result> ])
(reg:SI 71 [ D.1234 ])) -1 (nil)
(nil))
(jump_insn 169 168 170 1 (set (pc)
(label_ref 173)) -1 (nil)
(nil))
;; End of basic block 1, registers live:
(nil)
(barrier 170 169 171)
(note 171 170 185 NOTE_INSN_FUNCTION_END)
;; Start of basic block 2, registers live: (nil)
(note 185 171 175 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(insn 175 185 176 2 (clobber (reg/i:SI 1 r1)) -1 (nil)
(nil))
(insn 176 175 177 2 (clobber (reg:SI 107 [ <result> ])) -1 (nil)
(nil))
(jump_insn 177 176 178 2 (set (pc)
(label_ref 179)) -1 (nil)
(nil))
;; End of basic block 2, registers live:
(nil)
(barrier 178 177 173)
;; Start of basic block 3, registers live: (nil)
(code_label 173 178 186 3 1 "" [1 uses])
(note 186 173 174 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 174 186 179 3 (set (reg/i:SI 1 r1)
(reg:SI 107 [ <result> ])) -1 (nil)
(nil))
;; End of basic block 3, registers live:
(nil)
;; Start of basic block 4, registers live: (nil)
(code_label 179 174 187 4 2 "" [1 uses])
(note 187 179 181 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn 181 187 182 4 (clobber (mem:BLK (scratch) [0 A8])) -1 (nil)
(nil))
(insn 182 181 183 4 (clobber (mem:BLK (reg/f:SI 29 r29) [0 A8])) -1 (nil)
(nil))
(insn 183 182 184 4 (set (reg/f:SI 29 r29)
(reg:SI 139)) -1 (nil)
(nil))
(insn 184 183 0 4 (use (reg/i:SI 1 r1)) -1 (nil)
(nil))
;; End of basic block 4, registers live:
(nil)
;; Function main (main)
Pass 0
Register 70 costs: GR_REGS:20000000 ALL_REGS:20000000 MEM:10004000
Register 71 costs: GR_REGS:10000000 ALL_REGS:10002000 MEM:8000
Register 72 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 73 costs: GR_REGS:20000000 ALL_REGS:20004000 MEM:10012000
Register 74 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 75 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 76 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 77 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 80 costs: GR_REGS:30004000 ALL_REGS:30014000 MEM:36000
Register 81 costs: GR_REGS:10000000 ALL_REGS:10002000 MEM:8000
Register 82 costs: GR_REGS:30004000 ALL_REGS:30014000 MEM:36000
Register 83 costs: GR_REGS:10000000 ALL_REGS:10002000 MEM:8000
Register 90 costs: GR_REGS:30004000 ALL_REGS:30014000 MEM:36000
Register 91 costs: GR_REGS:10000000 ALL_REGS:10002000 MEM:8000
Register 92 costs: GR_REGS:30004000 ALL_REGS:30014000 MEM:36000
Register 93 costs: GR_REGS:10000000 ALL_REGS:10002000 MEM:8000
Register 97 costs: GR_REGS:0 ALL_REGS:8000 MEM:16000
Register 98 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 99 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 106 costs: GR_REGS:0 ALL_REGS:10000 MEM:20000
Register 107 costs: GR_REGS:20000000 ALL_REGS:20000000 MEM:10004000
Register 108 costs: GR_REGS:20000000 ALL_REGS:20000000 MEM:10004000
Register 109 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 113 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 114 costs: GR_REGS:20004000 ALL_REGS:20008000 MEM:20000
Register 115 costs: GR_REGS:20004000 ALL_REGS:20008000 MEM:20000
Register 116 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 120 costs: GR_REGS:20004000 ALL_REGS:20008000 MEM:20000
Register 121 costs: GR_REGS:20004000 ALL_REGS:20008000 MEM:20000
Register 122 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 126 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 127 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 128 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 129 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 130 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 131 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 132 costs: GR_REGS:10000000 ALL_REGS:10002000 MEM:8000
Register 133 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 134 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 135 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 136 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 137 costs: GR_REGS:0 ALL_REGS:4000 MEM:8000
Register 139 costs: GR_REGS:20000000 ALL_REGS:20000000 MEM:20000000
Register 65 pref GR_REGS or none
Register 66 pref GR_REGS or none
Register 67 pref GR_REGS or none
Register 68 pref GR_REGS or none
Register 69 pref GR_REGS or none
Register 70 pref GR_REGS or none
Register 71 pref GR_REGS or none
Register 72 pref GR_REGS
Register 73 pref GR_REGS or none
Register 74 pref GR_REGS
Register 75 pref GR_REGS
Register 76 pref GR_REGS
Register 77 pref GR_REGS
Register 78 pref GR_REGS or none
Register 79 pref GR_REGS or none
Register 80 pref GR_REGS or none
Register 81 pref GR_REGS or none
Register 82 pref GR_REGS or none
Register 83 pref GR_REGS or none
Register 84 pref GR_REGS or none
Register 85 pref GR_REGS or none
Register 86 pref GR_REGS or none
Register 87 pref GR_REGS or none
Register 88 pref GR_REGS or none
Register 89 pref GR_REGS or none
Register 90 pref GR_REGS or none
Register 91 pref GR_REGS or none
Register 92 pref GR_REGS or none
Register 93 pref GR_REGS or none
Register 94 pref GR_REGS or none
Register 95 pref GR_REGS or none
Register 96 pref GR_REGS or none
Register 97 pref GR_REGS
Register 98 pref GR_REGS
Register 99 pref GR_REGS
Register 100 pref GR_REGS or none
Register 101 pref GR_REGS or none
Register 102 pref GR_REGS or none
Register 103 pref GR_REGS or none
Register 104 pref GR_REGS or none
Register 105 pref GR_REGS or none
Register 106 pref GR_REGS
Register 107 pref GR_REGS or none
Register 108 pref GR_REGS or none
Register 109 pref GR_REGS
Register 110 pref GR_REGS or none
Register 111 pref GR_REGS or none
Register 112 pref GR_REGS or none
Register 113 pref GR_REGS
Register 114 pref GR_REGS or none
Register 115 pref GR_REGS or none
Register 116 pref GR_REGS
Register 117 pref GR_REGS or none
Register 118 pref GR_REGS or none
Register 119 pref GR_REGS or none
Register 120 pref GR_REGS or none
Register 121 pref GR_REGS or none
Register 122 pref GR_REGS
Register 123 pref GR_REGS or none
Register 124 pref GR_REGS or none
Register 125 pref GR_REGS or none
Register 126 pref GR_REGS
Register 127 pref GR_REGS
Register 128 pref GR_REGS
Register 129 pref GR_REGS
Register 130 pref GR_REGS
Register 131 pref GR_REGS
Register 132 pref GR_REGS or none
Register 133 pref GR_REGS
Register 134 pref GR_REGS
Register 135 pref GR_REGS
Register 136 pref GR_REGS
Register 137 pref GR_REGS
Register 138 pref GR_REGS or none
Register 139 pref GR_REGS or none
140 registers.
Register 70 used 2 times across 91 insns in block 0; set 1 time; crosses 2
calls; GR_REGS or none; pointer.
Register 71 used 2 times across 5 insns in block 0; set 1 time; GR_REGS or none.
Register 72 used 2 times across 3 insns in block 0; set 1 time.
Register 73 used 4 times across 4 insns in block 0; set 2 times; dies in 2
places; GR_REGS or none; pointer.
Register 74 used 2 times across 2 insns in block 0; set 1 time.
Register 75 used 2 times across 2 insns in block 0; set 1 time.
Register 76 used 2 times across 2 insns in block 0; set 1 time.
Register 77 used 2 times across 3 insns in block 0; set 1 time.
Register 80 used 14 times across 20 insns in block 0; set 6 times; dies in 2
places; 8 bytes; GR_REGS or none.
Register 81 used 2 times across 3 insns in block 0; set 1 time; GR_REGS or none.
Register 82 used 14 times across 28 insns in block 0; set 6 times; dies in 2
places; 8 bytes; GR_REGS or none.
Register 83 used 2 times across 3 insns in block 0; set 1 time; GR_REGS or none.
Register 90 used 14 times across 20 insns in block 0; set 6 times; dies in 2
places; 8 bytes; GR_REGS or none.
Register 91 used 2 times across 3 insns in block 0; set 1 time; GR_REGS or none.
Register 92 used 14 times across 28 insns in block 0; set 6 times; dies in 2
places; 8 bytes; GR_REGS or none.
Register 93 used 2 times across 3 insns in block 0; set 1 time; GR_REGS or none.
Register 97 used 4 times across 61 insns in block 0; set 1 time; crosses 2
calls; 2 bytes.
Register 98 used 2 times across 77 insns in block 0; set 1 time; crosses 2
calls.
Register 99 used 2 times across 2 insns in block 0; set 1 time.
Register 106 used 5 times across 64 insns in block 0; set 1 time; crosses 2
calls; 2 bytes.
Register 107 used 2 times across 2 insns in block 0; set 1 time; GR_REGS or
none.
Register 108 used 2 times across 2 insns in block 0; set 1 time; GR_REGS or
none; pointer.
Register 109 used 2 times across 2 insns in block 0; set 1 time; pointer.
Register 113 used 2 times across 2 insns in block 0; set 1 time; pointer.
Register 114 used 7 times across 8 insns in block 0; set 3 times; 8 bytes;
GR_REGS or none.
Register 115 used 7 times across 8 insns in block 0; set 3 times; 8 bytes;
GR_REGS or none.
Register 116 used 2 times across 3 insns in block 0; set 1 time; pointer.
Register 120 used 7 times across 8 insns in block 0; set 3 times; 8 bytes;
GR_REGS or none.
Register 121 used 7 times across 8 insns in block 0; set 3 times; 8 bytes;
GR_REGS or none.
Register 122 used 2 times across 3 insns in block 0; set 1 time; pointer.
Register 126 used 2 times across 2 insns in block 0; set 1 time.
Register 127 used 2 times across 2 insns in block 0; set 1 time.
Register 128 used 2 times across 2 insns in block 0; set 1 time.
Register 129 used 2 times across 2 insns in block 0; set 1 time.
Register 130 used 2 times across 2 insns in block 0; set 1 time; pointer.
Register 131 used 2 times across 2 insns in block 0; set 1 time.
Register 132 used 2 times across 2 insns in block 0; set 1 time; GR_REGS or
none.
Register 133 used 2 times across 3 insns in block 0; set 1 time; pointer.
Register 134 used 2 times across 2 insns in block 0; set 1 time.
Register 135 used 2 times across 2 insns in block 0; set 1 time.
Register 136 used 2 times across 3 insns in block 0; set 1 time; pointer.
Register 137 used 2 times across 2 insns in block 0; set 1 time.
Register 139 used 2 times across 99 insns in block 0; set 1 time; crosses 3
calls; GR_REGS or none; pointer.
1 basic blocks, 2 edges.
Basic block 0 prev -1, next -2, loop_depth 0, count 0, freq 0.
Predecessors: ENTRY (fallthru)
Successors: EXIT [100.0%] (fallthru)
Registers live at start: 29 [r29] 30 [r30]
Registers live at end: 1 [r1] 29 [r29] 30 [r30]
;; Register 70 in 5.
;; Register 71 in 1.
;; Register 72 in 1.
;; Register 74 in 1.
;; Register 75 in 1.
;; Register 76 in 1.
;; Register 77 in 2.
;; Register 81 in 1.
;; Register 83 in 1.
;; Register 91 in 1.
;; Register 93 in 1.
;; Register 97 in 8.
;; Register 98 in 7.
;; Register 99 in 1.
;; Register 106 in 6.
;; Register 107 in 1.
;; Register 108 in 1.
;; Register 109 in 1.
;; Register 113 in 1.
;; Register 114 in 2.
;; Register 115 in 2.
;; Register 116 in 1.
;; Register 120 in 2.
;; Register 121 in 2.
;; Register 122 in 1.
;; Register 126 in 1.
;; Register 127 in 1.
;; Register 128 in 1.
;; Register 129 in 1.
;; Register 130 in 1.
;; Register 131 in 1.
;; Register 132 in 1.
;; Register 133 in 2.
;; Register 134 in 1.
;; Register 135 in 1.
;; Register 136 in 2.
;; Register 137 in 1.
;; Register 139 in 4.
(note 2 0 6 NOTE_INSN_DELETED)
;; Start of basic block 0, registers live: 29 [r29] 30 [r30]
(note 6 2 3 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(note 3 6 180 0 NOTE_INSN_FUNCTION_BEG)
(insn 180 3 5 0 (set (reg/f:SI 139)
(reg/f:SI 29 r29 [ saved_stack3 ])) 40 {movsi_general} (nil)
(nil))
(call_insn 5 180 8 0 (parallel [
(call (mem:QI (symbol_ref:SI ("__main") [flags 0x41]) [0 S1 A8])
(const_int 0 [0x0]))
(clobber (reg:SI 31 r31))
]) 49 {call} (nil)
(expr_list:REG_UNUSED (reg:SI 31 r31)
(expr_list:REG_UNUSED (reg:SI 31 r31)
(expr_list:REG_EH_REGION (const_int 0 [0x0])
(nil))))
(nil))
(insn 8 5 9 0 (set (reg/f:SI 108)
(reg/f:SI 29 r29 [ saved_stack3 ])) 40 {movsi_general} (nil)
(nil))
(insn 9 8 11 0 (set (reg/f:SI 70 [ saved_stack3 ])
(reg/f:SI 108)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg/f:SI 108)
(nil)))
(insn 11 9 12 0 (set (reg/f:SI 109)
(symbol_ref:SI ("c") [flags 0x2] <var_decl 0x3adb3108 c>)) 40
{movsi_general} (nil)
(nil))
(insn 12 11 37 0 (set (reg:HI 106 [ c0 ])
(mem/c/i:HI (reg/f:SI 109) [0 c+0 S2 A16])) 41 {movhi_general} (nil)
(expr_list:REG_DEAD (reg/f:SI 109)
(nil)))
(insn 37 12 38 0 (set (reg:SI 99 [ D.1205 ])
(sign_extend:SI (reg:HI 106 [ c0 ]))) 37 {extendhisi2} (nil)
(nil))
(insn 38 37 39 0 (set (reg:SI 98 [ D.1206 ])
(ashift:SI (reg:SI 99 [ D.1205 ])
(const_int 2 [0x2]))) 19 {ashlsi3} (nil)
(expr_list:REG_DEAD (reg:SI 99 [ D.1205 ])
(nil)))
(insn 39 38 40 0 (set (reg/f:SI 113)
(symbol_ref:SI ("b") [flags 0x2] <var_decl 0x3adb30b0 b>)) 40
{movsi_general} (nil)
(nil))
(insn 40 39 44 0 (set (reg:HI 97 [ b1 ])
(mem/c/i:HI (reg/f:SI 113) [0 b+0 S2 A16])) 41 {movhi_general} (nil)
(expr_list:REG_DEAD (reg/f:SI 113)
(nil)))
(insn 44 40 47 0 (set (reg:SI 93 [ D.1211 ])
(sign_extend:SI (reg:HI 106 [ c0 ]))) 37 {extendhisi2} (nil)
(nil))
(insn 47 44 45 0 (clobber (reg:DI 92 [ D.1212 ])) -1 (nil)
(insn_list:REG_LIBCALL 46 (nil)))
(insn 45 47 46 0 (set (subreg:SI (reg:DI 92 [ D.1212 ]) 4)
(reg:SI 93 [ D.1211 ])) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:SI 93 [ D.1211 ])
(expr_list:REG_NO_CONFLICT (reg:SI 93 [ D.1211 ])
(nil))))
(insn 46 45 50 0 (set (subreg:SI (reg:DI 92 [ D.1212 ]) 0)
(const_int 0 [0x0])) 40 {movsi_general} (nil)
(insn_list:REG_RETVAL 47 (expr_list:REG_NO_CONFLICT (reg:SI 93 [ D.1211 ])
(nil))))
(insn 50 46 48 0 (clobber (reg:DI 114)) -1 (nil)
(insn_list:REG_LIBCALL 49 (nil)))
(insn 48 50 49 0 (set (subreg:SI (reg:DI 114) 0)
(and:SI (subreg:SI (reg:DI 92 [ D.1212 ]) 0)
(const_int 15 [0xf]))) 10 {andsi3} (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 92 [ D.1212 ])
(nil)))
(insn 49 48 53 0 (set (subreg:SI (reg:DI 114) 4)
(and:SI (subreg:SI (reg:DI 92 [ D.1212 ]) 4)
(const_int -1 [0xffffffff]))) 10 {andsi3} (nil)
(expr_list:REG_DEAD (reg:DI 92 [ D.1212 ])
(insn_list:REG_RETVAL 50 (expr_list:REG_NO_CONFLICT (reg:DI 92 [ D.1212
])
(nil)))))
(insn 53 49 51 0 (clobber (reg:DI 92 [ D.1212 ])) -1 (nil)
(nil))
(insn 51 53 52 0 (set (subreg:SI (reg:DI 92 [ D.1212 ]) 0)
(subreg:SI (reg:DI 114) 0)) 40 {movsi_general} (nil)
(nil))
(insn 52 51 54 0 (set (subreg:SI (reg:DI 92 [ D.1212 ]) 4)
(subreg:SI (reg:DI 114) 4)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:DI 114)
(nil)))
(insn 54 52 57 0 (set (reg:SI 91 [ D.1213 ])
(sign_extend:SI (reg:HI 97 [ b1 ]))) 37 {extendhisi2} (nil)
(nil))
(insn 57 54 55 0 (clobber (reg:DI 90 [ D.1214 ])) -1 (nil)
(insn_list:REG_LIBCALL 56 (nil)))
(insn 55 57 56 0 (set (subreg:SI (reg:DI 90 [ D.1214 ]) 4)
(reg:SI 91 [ D.1213 ])) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:SI 91 [ D.1213 ])
(expr_list:REG_NO_CONFLICT (reg:SI 91 [ D.1213 ])
(nil))))
(insn 56 55 60 0 (set (subreg:SI (reg:DI 90 [ D.1214 ]) 0)
(const_int 0 [0x0])) 40 {movsi_general} (nil)
(insn_list:REG_RETVAL 57 (expr_list:REG_NO_CONFLICT (reg:SI 91 [ D.1213 ])
(nil))))
(insn 60 56 58 0 (clobber (reg:DI 115)) -1 (nil)
(insn_list:REG_LIBCALL 59 (nil)))
(insn 58 60 59 0 (set (subreg:SI (reg:DI 115) 0)
(and:SI (subreg:SI (reg:DI 90 [ D.1214 ]) 0)
(const_int 15 [0xf]))) 10 {andsi3} (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 90 [ D.1214 ])
(nil)))
(insn 59 58 63 0 (set (subreg:SI (reg:DI 115) 4)
(and:SI (subreg:SI (reg:DI 90 [ D.1214 ]) 4)
(const_int -1 [0xffffffff]))) 10 {andsi3} (nil)
(expr_list:REG_DEAD (reg:DI 90 [ D.1214 ])
(insn_list:REG_RETVAL 60 (expr_list:REG_NO_CONFLICT (reg:DI 90 [ D.1214
])
(nil)))))
(insn 63 59 61 0 (clobber (reg:DI 90 [ D.1214 ])) -1 (nil)
(nil))
(insn 61 63 62 0 (set (subreg:SI (reg:DI 90 [ D.1214 ]) 0)
(subreg:SI (reg:DI 115) 0)) 40 {movsi_general} (nil)
(nil))
(insn 62 61 64 0 (set (subreg:SI (reg:DI 90 [ D.1214 ]) 4)
(subreg:SI (reg:DI 115) 4)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:DI 115)
(nil)))
(insn 64 62 65 0 (set (reg/f:SI 116)
(plus:SI (reg/f:SI 30 r30)
(const_int -24 [0xffffffe8]))) 8 {addsi3} (nil)
(nil))
(insn 65 64 66 0 (set (reg/f:SI 29 r29 [ saved_stack3 ])
(plus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(const_int -24 [0xffffffe8]))) 8 {addsi3} (nil)
(nil))
(insn 66 65 67 0 (set (mem:SI (reg/f:SI 29 r29 [ saved_stack3 ]) [0 S4 A32])
(reg/f:SI 116)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg/f:SI 116)
(nil)))
(insn 67 66 68 0 (set (mem:SI (plus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(const_int 8 [0x8])) [0 S4 A32])
(subreg:SI (reg:DI 92 [ D.1212 ]) 0)) 40 {movsi_general} (nil)
(nil))
(insn 68 67 69 0 (set (mem:SI (plus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(const_int 12 [0xc])) [0 S4 A32])
(subreg:SI (reg:DI 92 [ D.1212 ]) 4)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:DI 92 [ D.1212 ])
(nil)))
(insn 69 68 70 0 (set (mem:SI (plus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(const_int 16 [0x10])) [0 S4 A32])
(subreg:SI (reg:DI 90 [ D.1214 ]) 0)) 40 {movsi_general} (nil)
(nil))
(insn 70 69 71 0 (set (mem:SI (plus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(const_int 20 [0x14])) [0 S4 A32])
(subreg:SI (reg:DI 90 [ D.1214 ]) 4)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:DI 90 [ D.1214 ])
(nil)))
(call_insn 71 70 72 0 (parallel [
(call (mem:QI (symbol_ref:SI ("__muldi3") [flags 0x41]) [0 S1 A8])
(const_int 24 [0x18]))
(clobber (reg:SI 31 r31))
]) 49 {call} (nil)
(expr_list:REG_UNUSED (reg:SI 31 r31)
(expr_list:REG_UNUSED (reg:SI 31 r31)
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))))
(nil))
(insn 72 71 94 0 (set (reg/f:SI 29 r29 [ saved_stack3 ])
(plus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(const_int 24 [0x18]))) 8 {addsi3} (nil)
(nil))
(insn 94 72 97 0 (set (reg:SI 83 [ D.1221 ])
(sign_extend:SI (reg:HI 106 [ c0 ]))) 37 {extendhisi2} (nil)
(nil))
(insn 97 94 95 0 (clobber (reg:DI 82 [ D.1222 ])) -1 (nil)
(insn_list:REG_LIBCALL 96 (nil)))
(insn 95 97 96 0 (set (subreg:SI (reg:DI 82 [ D.1222 ]) 4)
(reg:SI 83 [ D.1221 ])) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:SI 83 [ D.1221 ])
(expr_list:REG_NO_CONFLICT (reg:SI 83 [ D.1221 ])
(nil))))
(insn 96 95 100 0 (set (subreg:SI (reg:DI 82 [ D.1222 ]) 0)
(const_int 0 [0x0])) 40 {movsi_general} (nil)
(insn_list:REG_RETVAL 97 (expr_list:REG_NO_CONFLICT (reg:SI 83 [ D.1221 ])
(nil))))
(insn 100 96 98 0 (clobber (reg:DI 120)) -1 (nil)
(insn_list:REG_LIBCALL 99 (nil)))
(insn 98 100 99 0 (set (subreg:SI (reg:DI 120) 0)
(and:SI (subreg:SI (reg:DI 82 [ D.1222 ]) 0)
(const_int 15 [0xf]))) 10 {andsi3} (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 82 [ D.1222 ])
(nil)))
(insn 99 98 103 0 (set (subreg:SI (reg:DI 120) 4)
(and:SI (subreg:SI (reg:DI 82 [ D.1222 ]) 4)
(const_int -1 [0xffffffff]))) 10 {andsi3} (nil)
(expr_list:REG_DEAD (reg:DI 82 [ D.1222 ])
(insn_list:REG_RETVAL 100 (expr_list:REG_NO_CONFLICT (reg:DI 82 [
D.1222 ])
(nil)))))
(insn 103 99 101 0 (clobber (reg:DI 82 [ D.1222 ])) -1 (nil)
(nil))
(insn 101 103 102 0 (set (subreg:SI (reg:DI 82 [ D.1222 ]) 0)
(subreg:SI (reg:DI 120) 0)) 40 {movsi_general} (nil)
(nil))
(insn 102 101 104 0 (set (subreg:SI (reg:DI 82 [ D.1222 ]) 4)
(subreg:SI (reg:DI 120) 4)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:DI 120)
(nil)))
(insn 104 102 107 0 (set (reg:SI 81 [ D.1223 ])
(sign_extend:SI (reg:HI 97 [ b1 ]))) 37 {extendhisi2} (nil)
(nil))
(insn 107 104 105 0 (clobber (reg:DI 80 [ D.1224 ])) -1 (nil)
(insn_list:REG_LIBCALL 106 (nil)))
(insn 105 107 106 0 (set (subreg:SI (reg:DI 80 [ D.1224 ]) 4)
(reg:SI 81 [ D.1223 ])) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:SI 81 [ D.1223 ])
(expr_list:REG_NO_CONFLICT (reg:SI 81 [ D.1223 ])
(nil))))
(insn 106 105 110 0 (set (subreg:SI (reg:DI 80 [ D.1224 ]) 0)
(const_int 0 [0x0])) 40 {movsi_general} (nil)
(insn_list:REG_RETVAL 107 (expr_list:REG_NO_CONFLICT (reg:SI 81 [ D.1223 ])
(nil))))
(insn 110 106 108 0 (clobber (reg:DI 121)) -1 (nil)
(insn_list:REG_LIBCALL 109 (nil)))
(insn 108 110 109 0 (set (subreg:SI (reg:DI 121) 0)
(and:SI (subreg:SI (reg:DI 80 [ D.1224 ]) 0)
(const_int 15 [0xf]))) 10 {andsi3} (nil)
(expr_list:REG_NO_CONFLICT (reg:DI 80 [ D.1224 ])
(nil)))
(insn 109 108 113 0 (set (subreg:SI (reg:DI 121) 4)
(and:SI (subreg:SI (reg:DI 80 [ D.1224 ]) 4)
(const_int -1 [0xffffffff]))) 10 {andsi3} (nil)
(expr_list:REG_DEAD (reg:DI 80 [ D.1224 ])
(insn_list:REG_RETVAL 110 (expr_list:REG_NO_CONFLICT (reg:DI 80 [
D.1224 ])
(nil)))))
(insn 113 109 111 0 (clobber (reg:DI 80 [ D.1224 ])) -1 (nil)
(nil))
(insn 111 113 112 0 (set (subreg:SI (reg:DI 80 [ D.1224 ]) 0)
(subreg:SI (reg:DI 121) 0)) 40 {movsi_general} (nil)
(nil))
(insn 112 111 114 0 (set (subreg:SI (reg:DI 80 [ D.1224 ]) 4)
(subreg:SI (reg:DI 121) 4)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:DI 121)
(nil)))
(insn 114 112 115 0 (set (reg/f:SI 122)
(plus:SI (reg/f:SI 30 r30)
(const_int -24 [0xffffffe8]))) 8 {addsi3} (nil)
(nil))
(insn 115 114 116 0 (set (reg/f:SI 29 r29 [ saved_stack3 ])
(plus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(const_int -24 [0xffffffe8]))) 8 {addsi3} (nil)
(nil))
(insn 116 115 117 0 (set (mem:SI (reg/f:SI 29 r29 [ saved_stack3 ]) [0 S4 A32])
(reg/f:SI 122)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg/f:SI 122)
(nil)))
(insn 117 116 118 0 (set (mem:SI (plus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(const_int 8 [0x8])) [0 S4 A32])
(subreg:SI (reg:DI 82 [ D.1222 ]) 0)) 40 {movsi_general} (nil)
(nil))
(insn 118 117 119 0 (set (mem:SI (plus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(const_int 12 [0xc])) [0 S4 A32])
(subreg:SI (reg:DI 82 [ D.1222 ]) 4)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:DI 82 [ D.1222 ])
(nil)))
(insn 119 118 120 0 (set (mem:SI (plus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(const_int 16 [0x10])) [0 S4 A32])
(subreg:SI (reg:DI 80 [ D.1224 ]) 0)) 40 {movsi_general} (nil)
(nil))
(insn 120 119 121 0 (set (mem:SI (plus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(const_int 20 [0x14])) [0 S4 A32])
(subreg:SI (reg:DI 80 [ D.1224 ]) 4)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:DI 80 [ D.1224 ])
(nil)))
(call_insn 121 120 122 0 (parallel [
(call (mem:QI (symbol_ref:SI ("__muldi3") [flags 0x41]) [0 S1 A8])
(const_int 24 [0x18]))
(clobber (reg:SI 31 r31))
]) 49 {call} (nil)
(expr_list:REG_UNUSED (reg:SI 31 r31)
(expr_list:REG_UNUSED (reg:SI 31 r31)
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))))
(nil))
(insn 122 121 140 0 (set (reg/f:SI 29 r29 [ saved_stack3 ])
(plus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(const_int 24 [0x18]))) 8 {addsi3} (nil)
(nil))
(insn 140 122 141 0 (set (reg:SI 77 [ D.1227 ])
(sign_extend:SI (reg:HI 106 [ c0 ]))) 37 {extendhisi2} (nil)
(expr_list:REG_DEAD (reg:HI 106 [ c0 ])
(nil)))
(insn 141 140 142 0 (set (reg:SI 76 [ D.1228 ])
(sign_extend:SI (reg:HI 97 [ b1 ]))) 37 {extendhisi2} (nil)
(expr_list:REG_DEAD (reg:HI 97 [ b1 ])
(nil)))
(insn 142 141 143 0 (parallel [
(set (reg:SI 75 [ D.1229 ])
(mult:SI (reg:SI 77 [ D.1227 ])
(reg:SI 76 [ D.1228 ])))
(clobber (scratch:SF))
(clobber (scratch:SF))
]) 22 {mulsi3} (nil)
(expr_list:REG_UNUSED (scratch:SF)
(expr_list:REG_UNUSED (scratch:SF)
(expr_list:REG_DEAD (reg:SI 77 [ D.1227 ])
(expr_list:REG_DEAD (reg:SI 76 [ D.1228 ])
(expr_list:REG_UNUSED (scratch:SF)
(expr_list:REG_UNUSED (scratch:SF)
(nil))))))))
(insn 143 142 144 0 (set (reg:SI 74 [ D.1230 ])
(ashift:SI (reg:SI 75 [ D.1229 ])
(const_int 2 [0x2]))) 19 {ashlsi3} (nil)
(expr_list:REG_DEAD (reg:SI 75 [ D.1229 ])
(nil)))
(insn 144 143 145 0 (set (reg:SI 126)
(plus:SI (reg:SI 74 [ D.1230 ])
(const_int 7 [0x7]))) 8 {addsi3} (nil)
(expr_list:REG_DEAD (reg:SI 74 [ D.1230 ])
(nil)))
(insn 145 144 146 0 (set (reg:SI 127)
(plus:SI (reg:SI 126)
(const_int 7 [0x7]))) 8 {addsi3} (nil)
(expr_list:REG_DEAD (reg:SI 126)
(nil)))
(insn 146 145 147 0 (set (reg:SI 128)
(lshiftrt:SI (reg:SI 127)
(const_int 3 [0x3]))) 21 {lshrsi3} (nil)
(expr_list:REG_DEAD (reg:SI 127)
(expr_list:REG_EQUAL (udiv:SI (reg:SI 127)
(const_int 8 [0x8]))
(nil))))
(insn 147 146 148 0 (set (reg:SI 129)
(ashift:SI (reg:SI 128)
(const_int 3 [0x3]))) 19 {ashlsi3} (nil)
(expr_list:REG_DEAD (reg:SI 128)
(nil)))
(insn 148 147 149 0 (set (reg/f:SI 29 r29 [ saved_stack3 ])
(minus:SI (reg/f:SI 29 r29 [ saved_stack3 ])
(reg:SI 129))) 9 {subsi3} (nil)
(expr_list:REG_DEAD (reg:SI 129)
(nil)))
(insn 149 148 150 0 (set (reg/f:SI 73 [ D.1232 ])
(reg/f:SI 29 r29 [ saved_stack3 ])) 40 {movsi_general} (nil)
(nil))
(insn 150 149 151 0 (set (reg/f:SI 130)
(plus:SI (reg/f:SI 73 [ D.1232 ])
(const_int 7 [0x7]))) 8 {addsi3} (nil)
(expr_list:REG_DEAD (reg/f:SI 73 [ D.1232 ])
(nil)))
(insn 151 150 152 0 (set (reg:SI 131)
(lshiftrt:SI (reg/f:SI 130)
(const_int 3 [0x3]))) 21 {lshrsi3} (nil)
(expr_list:REG_DEAD (reg/f:SI 130)
(expr_list:REG_EQUAL (udiv:SI (reg/f:SI 130)
(const_int 8 [0x8]))
(nil))))
(insn 152 151 153 0 (set (reg:SI 132)
(ashift:SI (reg:SI 131)
(const_int 3 [0x3]))) 19 {ashlsi3} (nil)
(expr_list:REG_DEAD (reg:SI 131)
(nil)))
(insn 153 152 154 0 (set (reg/f:SI 73 [ D.1232 ])
(reg:SI 132)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:SI 132)
(nil)))
(insn 154 153 156 0 (set (mem/c/i:SI (plus:SI (reg/f:SI 30 r30)
(const_int -12 [0xfffffff4])) [0 a2+0 S4 A32])
(reg/f:SI 73 [ D.1232 ])) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg/f:SI 73 [ D.1232 ])
(nil)))
(insn 156 154 157 0 (set (reg:SI 72 [ D.1233 ])
(lshiftrt:SI (reg:SI 98 [ D.1206 ])
(const_int 2 [0x2]))) 21 {lshrsi3} (nil)
(expr_list:REG_DEAD (reg:SI 98 [ D.1206 ])
(expr_list:REG_EQUAL (udiv:SI (reg:SI 98 [ D.1206 ])
(const_int 4 [0x4]))
(nil))))
(insn 157 156 158 0 (set (reg/f:SI 133 [ a2 ])
(mem/c/i:SI (plus:SI (reg/f:SI 30 r30)
(const_int -12 [0xfffffff4])) [0 a2+0 S4 A32])) 40
{movsi_general} (nil)
(nil))
(insn 158 157 159 0 (set (reg:SI 134)
(ashift:SI (reg:SI 72 [ D.1233 ])
(const_int 2 [0x2]))) 19 {ashlsi3} (nil)
(expr_list:REG_DEAD (reg:SI 72 [ D.1233 ])
(nil)))
(insn 159 158 160 0 (set (reg:SI 135)
(plus:SI (reg:SI 134)
(reg/f:SI 133 [ a2 ]))) 8 {addsi3} (nil)
(expr_list:REG_DEAD (reg:SI 134)
(expr_list:REG_DEAD (reg/f:SI 133 [ a2 ])
(nil))))
(insn 160 159 161 0 (set (reg/f:SI 136)
(plus:SI (reg:SI 135)
(const_int 4 [0x4]))) 8 {addsi3} (nil)
(expr_list:REG_DEAD (reg:SI 135)
(nil)))
(insn 161 160 162 0 (set (reg:SI 137)
(const_int 5 [0x5])) 40 {movsi_general} (nil)
(nil))
(insn 162 161 164 0 (set (mem/s/j:SI (reg/f:SI 136) [0 S4 A32])
(reg:SI 137)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:SI 137)
(expr_list:REG_DEAD (reg/f:SI 136)
(nil))))
(insn 164 162 165 0 (set (reg:SI 71 [ D.1234 ])
(const_int 0 [0x0])) 40 {movsi_general} (nil)
(nil))
(insn 165 164 166 0 (clobber (mem:BLK (scratch) [0 A8])) -1 (nil)
(nil))
(insn 166 165 167 0 (clobber (mem:BLK (reg/f:SI 29 r29 [ saved_stack3 ]) [0
A8])) -1 (nil)
(nil))
(insn 167 166 168 0 (set (reg/f:SI 29 r29 [ saved_stack3 ])
(reg/f:SI 70 [ saved_stack3 ])) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg/f:SI 70 [ saved_stack3 ])
(nil)))
(insn 168 167 171 0 (set (reg:SI 107 [ <result> ])
(reg:SI 71 [ D.1234 ])) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:SI 71 [ D.1234 ])
(nil)))
(note 171 168 174 0 NOTE_INSN_FUNCTION_END)
(insn 174 171 181 0 (set (reg/i:SI 1 r1 [ <result> ])
(reg:SI 107 [ <result> ])) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg:SI 107 [ <result> ])
(nil)))
(insn 181 174 182 0 (clobber (mem:BLK (scratch) [0 A8])) -1 (nil)
(nil))
(insn 182 181 183 0 (clobber (mem:BLK (reg/f:SI 29 r29 [ saved_stack3 ]) [0
A8])) -1 (nil)
(nil))
(insn 183 182 184 0 (set (reg/f:SI 29 r29 [ saved_stack3 ])
(reg/f:SI 139)) 40 {movsi_general} (nil)
(expr_list:REG_DEAD (reg/f:SI 139)
(nil)))
(insn 184 183 0 0 (use (reg/i:SI 1 r1 [ <result> ])) -1 (nil)
(nil))
;; End of basic block 0, registers live:
1 [r1] 29 [r29] 30 [r30]
;; Function main (main)
Spilling for insn 45.
