Hi, We were looking at the implementation of vcond for altivec and we have a couple of questions.
vcond<type> has 6 operands, rs6000_emit_vector_cond_expr is called from define_expand for "vcond<type>". It gets those operands in their original order, as in vcond, and emits op0 = (op4 cond op5 ? op1 : op2), where cond is op3. Here is vcond for vector short (vconduv8hi, vcondv16qi, and vconduv16qi are similar): (define_expand "vcondv8hi" [(set (match_operand:V4SF 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V8HI 2 "register_operand" "v") (match_operand:V8HI 3 "comparison_operator" "") (match_operand:V8HI 4 "register_operand" "v") (match_operand:V8HI 5 "register_operand" "v") ] UNSPEC_VCOND_V8HI))] "TARGET_ALTIVEC" " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; } ") Is there a reason why op0 is V4SF and op1 is V4SI (and not V8HI)? In V4SF, op1 is V4SI: (define_expand "vcondv4sf" [(set (match_operand:V4SF 0 "register_operand" "=v") (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") (match_operand:V4SF 2 "register_operand" "v") (match_operand:V4SF 3 "comparison_operator" "") (match_operand:V4SF 4 "register_operand" "v") (match_operand:V4SF 5 "register_operand" "v") ] UNSPEC_VCOND_V4SF))] "TARGET_ALTIVEC" " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], operands[3], operands[4], operands[5])) DONE; else FAIL; } ") Same question: is there a reason for op1 to be V4SI? And also, why not use if_then_else instead of unspec (in all vcond's)? Thanks, Sa and Ira