Paul Brook <[EMAIL PROTECTED]> writes: > > > 1. Is there a way to check for dependency b/w this two instructions. > > > 2. Any existing backend that has this type of design. > > > > gcc currently does a relatively crummy job of handling this type of > > VLIW architecture. You can describe the dependencies in the > > scheduler, but the scheduler won't insert any required nops for you. > > The usual approach is walk through the insn chain in the MD reorg pass > > and insert nops at that time. For example, look at mips_reorg in > > config/mips/mips.c. I've also done it in FINAL_PRESCAN_INSN. > > Given you only have limited dual-issue, could the delay slot mechanisms be > used for this?
Sure, I've done that too, but you still have to insert the nops manually. That is what mips.c is doing. The delay slot mechanisms will fill in an insn if there is one, but they won't fill in a nop if there isn't an insn. Basically sched2 and subsequent passes need an overhaul to support VLIW systems. Ian
