Shekhar Divekar wrote:
(insn 5 4 6 0x0 (set (reg/v:SI 71)
        (ashiftrt:SI (reg/v:SI 71)
            (const_int 24 [0x18]))) -1 (nil)
    (nil))
This looks suspect.  You shouldn't be using the same input and output 
pseudo regs here.  You should instead generate a temporary for the 
output of the left shift, and use that as the input of the right shift. 
 That should at least help, since it means one less instruction that 
needs to be modified by put_var_into_stack.
There may also be other things wrong.

You would try looking at what other ports do. Your port is not the only RISC like port in gcc-3.3.x. So start building other random ports, and feeding in your testcase, and look at the RTL that they generate, and figure out why yours is different.
--
Jim Wilson, GNU Tools Support, http://www.specifix.com

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