I'm really shooting in the dark here, but my guess is that you have a
define_expand for movdi that is not reload safe. You can do this
operation correctly, you just have to reverse the instructions: load
a5 from (a4 + 4) before you load a4 from (a4). See, e.g.,
mips_split_64bit_move in mips.c and note the use of
reg_overlap_mentioned_p.
Sir, the following is a the part of .lreg dump file which is being
changed in .greg file.
(insn 29 28 31 6 (set (subreg:SI (reg:DI 34) 4)
(const_int 0 [0x0])) 17 {movsi_short_const} (nil)
(nil))
(insn 31 29 32 6 (parallel [
(set (reg:DI 28 [ D.1863 ])
(minus:DI (reg:DI 34)
(reg:DI 28 [ D.1863 ])))
(clobber (reg:CC 21 cc))
]) 33 {subdi3} (nil)
(expr_list:REG_UNUSED (reg:CC 21 cc)
(expr_list:REG_DEAD (reg:DI 34)
(expr_list:REG_UNUSED (reg:CC 21 cc)
(nil)))))
In greg pass some instructions are inserted between insns 29 and
31.These instruction are inserted by reload. In .greg file there is
spill code for insn 31, which is given below
Reloads for insn # 31
Reload 0: reload_in (SI) = (plus:SI (reg/f:SI 14 a6)
(const_int -16
[0xfffffff0]))
ADDR_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine
reload_in_reg: (plus:SI (reg/f:SI 14 a6)
(const_int -16
[0xfffffff0]))
reload_reg_rtx: (reg:SI 13 a5)
Reload 1: reload_in (SI) = (plus:SI (reg/f:SI 14 a6)
(const_int -16
[0xfffffff0]))
ADDR_REGS, RELOAD_FOR_INPUT_ADDRESS (opnum = 2), can't combine
reload_in_reg: (plus:SI (reg/f:SI 14 a6)
(const_int -16
[0xfffffff0]))
reload_reg_rtx: (reg:SI 12 a4)
Reload 2: reload_out (DI) = (mem/c:DI (plus:SI (reg/f:SI 14 a6)
(const_int -16
[0xfffffff0])) [0 D.1863+0 S8 A32])
GENERAL_REGS, RELOAD_OTHER (opnum = 0)
reload_out_reg: (reg:DI 28 [ D.1863 ])
reload_reg_rtx: (reg:DI 2 d2)
Reload 3: reload_in (DI) = (mem/c:DI (plus:SI (reg/f:SI 14 a6)
(const_int -16
[0xfffffff0])) [0 D.1863+0 S8 A32])
GENERAL_REGS, RELOAD_FOR_INPUT (opnum = 2), can't combine
reload_in_reg: (reg:DI 28 [ D.1863 ])
reload_reg_rtx: (reg:DI 12 a4)
I didnt understand what these means.
The following pattern is from .greg file
(insn 29 28 90 6 (set (reg:SI 1 d1 [orig:34+4 ] [34])
(const_int 0 [0x0])) 17 {movsi_short_const} (nil)
(nil))
(insn 90 29 91 6 (set (reg:SI 12 a4)
(const_int -16 [0xfffffff0])) 17 {movsi_short_const} (nil)
(nil))
(insn 91 90 94 6 (parallel [
(set (reg:SI 12 a4)
(plus:SI (reg:SI 12 a4)
(reg/f:SI 14 a6)))
(clobber (reg:CC 21 cc))
]) 29 {addsi3} (nil)
(expr_list:REG_EQUIV (plus:SI (reg/f:SI 14 a6)
(const_int -16 [0xfffffff0]))
(nil)))
(insn 94 91 95 6 (set (reg:SI 12 a4)
(mem/c:SI (reg:SI 12 a4) [0 D.1863+0 S4 A32])) 15 {movsi_load} (nil)
(nil))
(insn 95 94 31 6 (set (reg:SI 13 a5 [orig:12+4 ] [12])
(mem/c:SI (plus:SI (reg:SI 12 a4)
(const_int 4 [0x4])) [0 D.1863+4 S4 A32])) 15 {movsi_load} (nil)
(nil))
(insn 31 95 87 6 (parallel [
(set (reg:DI 2 d2)
(minus:DI (reg:DI 0 d0 [34])
(reg:DI 12 a4)))
(clobber (reg:CC 21 cc))
]) 33 {subdi3} (nil)
(nil))
As you can see insns 90,91,94 and 95 are inserted in this pass, and
the code goes wrong in insns 95/94
Why are these insns inserted in between ?
With only subdi3 and adddi3 pattern available in the md file, and no
other define_split or define_insns or define_expand for DI mode, how
can i control the instructions generated due to reload?
Regards,
Shafi
