--- Robert Dewar <[EMAIL PROTECTED]> wrote:
> Tzi-cker Chiueh wrote:
> > We have considered the bound instruction in the CASH project. But
> > we found that bound instruction is slower than the six normal
> > instructions it is meant to replace for range checking. For example, the
> > bound instruction on a 1.1 GHz PIII machine requires 7-8 clock cycles
> > while the 6 equivalent instructions require 6-7 clock cycles. We have not
> > tested it on newer processors, though.
>
> Might still be appropriate to use it in -Os mode I would think ...
The important thing here is probably the jump prediction subsystem of
some processors - i.e. some memory bits read/written at each conditionnal
jump (for instance addressed by the 4 low order address bits of the jcc
instruction for a 16 bits jump prediction system, encoding the last
result at this address). Very long pipeline processors like ia32 are
very sensitive to the rate of failed prediction.
I am just talking here of ia32, because ia64 does not have "bound" and it
has the predict-taken/predict-not-taken encoded in the jcc (by using segment
prefix on the jcc assembly instruction).
I assume that ia32 "bound" instruction is never predicted "taken", and does
not modify the prediction subsystem.
If you add few tens thousands "bound" instructions to a software that has
a 80% success rate of jump prediction, you slow it down by 7-8 times few
tens thousands (vague estimate assuming each assembly instruction has the
same probability to be executed).
If you add three times few tens thousands "test/jcc" instruction, you reduce
seriously the 80% success rate of jump prediction of your initial program
because of the added noise.
Basically, that means a real measure of the "test/jcc" versus "bound" timing
influence on a real application will worth the time spend.
By the way, someone knows how the jump prediction behaves on "jecxz" and "loop"
assembly instructions - i.e. is the prediction based on the current content
of %ecx register?
Etienne.
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