> I don't know whether any other chip has this particular limitation, > but it's not hard to handle. ashlsi3 and friends should be a > define_expand which turn an overly large CONST_INT into two shifts, > load the shift count into a register, whichever is likely to be > better. The MIPS16 does this, for example (search for any_shift:GPR > in mips.md). Then the real insn should use an operand predicate which > only accepts CONST_INTs which are in range.
I can handle the large constant shifts with multiple shift opcodes. The problem is, it can't handle large shifts counts in registers either. A 32 bit value can be shifted at most 16 bits in a single opcode, period. At the moment, the only solution I can see is to code constant shifts with multiple opcodes, and whenever I need a variable shift code a subroutine call instead which checks for out of range shifts. I was hoping there was an alternative, but I haven't seen anything that makes me think gcc will react nicely to failed shift expanders.
