On Thu, 6 Mar 2025, Andrew Pinski via Gcc wrote:
> > Why: I have the occasional need to have gcc emit MIPS1 instructions that do
> > not contain a subset of loads and stores (lwl/swl/lwr/swl instructions)
>
> The GCC patch to provide an option not emit lwl/lwr/swl/swr should be easily.
> Something like:
> ```
> diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
> index e224ade2a1a..c40cae1a530 100644
> --- a/gcc/config/mips/mips.h
> +++ b/gcc/config/mips/mips.h
> @@ -1191,7 +1191,8 @@ struct mips_cpu_info {
> && (MODE) == V2SFmode)) \
> && !TARGET_MIPS16)
>
> -#define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 \
> +#define ISA_HAS_LWL_LWR (mips_isa_rev <= 5
> \
> + && TARGET_LEFT_RIGHT \
> && (!TARGET_MIPS16 || ISA_HAS_MIPS16E2))
>
> #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5)
> diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt
> index e24565469d9..e9414765b06 100644
> --- a/gcc/config/mips/mips.opt
> +++ b/gcc/config/mips/mips.opt
> @@ -214,6 +214,10 @@ mfix4300
> Target Var(TARGET_4300_MUL_FIX)
> Work around an early 4300 hardware bug.
>
> +mleftright
> +Target Var(TARGET_LEFT_RIGHT) Init(1)
> +Emit the load/store left/right instruction if possible
Just: "Use load/store left/right instructions." I suppose, as with most
of such other options (I think it should be obvious to everyone that any
instructions are only produced by the compiler where it makes sense using
them). A complementing update to the manual would be required as well.
It might be good having it tied to a specific microarchitecture having
this limitation if applicable, so that one can configure it as a default
with no extra hassle needed (nobody has ever bothered to submit support
for `-march=lexra', not even now that the patent has expired so it would
be uncontroversial). Maybe it should actually be `-march=lexra' only,
without a separate machine option, to simplify interaction with binutils?
Otherwise there'll be a specs change required to control GAS accordingly
and it seems an overkill to me. We don't have explicit options for all
the various ISA subsets anyway.
> You could also in theory error out in GNU binutils as which can help.
Well, I think it should be a prerequisite for the GCC change and I'll be
happy to review such an update to binutils if properly submitted. Cases
such as this were exactly my motivation for commit 35d0a16941aa ("MIPS:
Opcode membership proposal"),
<https://inbox.sourceware.org/binutils/alpine.deb.1.10.1012181108290.4...@tp.orcam.me.uk/>,
which you were actually kind enough to review back in the day, so adding
support for `-march=lexra' to binutils ought to be a trivial task
nowadays.
> Accepting a patch to both I suspect will be acceptable upstream
> communities since there is little to no development on the MIPS
> backends and they are only now used for embedded/legacy developement.
Well, my time available is limited, but I try to keep the binutils port
in a shapely manner and even make improvements where opportunities are
identified. I have test setups with real hardware in place as well ready
to run at any time (sadly I've lost a piece of 64-bit hardware and have no
suitable replacement in place, so this has become a bit trickier for me;
I'm still half-heartedly chasing a possible replacement as the original
piece seems beyond repair owing to the lack of available parts).
I can't comment on the GCC port though.
Maciej
