This is a regression present on the mainline only, but the underlying issue
has been latent for years: the compiler and the assembler disagree on the
support of the VIS 3B SIMD ISA, the former bundling it with VIS 3 but not the
latter. IMO the documentation is not very clear, so this patch just aligns
the compiler with the assembler.
Bootstrapped/regtested on SPARC64/Solaris 11, applied on the mainline.
2025-01-18 Eric Botcazou <ebotca...@adacore.com>
PR target/118512
* config/sparc/sparc-c.cc (sparc_target_macros): Deal with VIS 3B.
* config/sparc/sparc.cc (dump_target_flag_bits): Likewise.
(sparc_option_override): Likewise.
(sparc_vis_init_builtins): Likewise.
* config/sparc/sparc.md (fpcmp_vis): Replace TARGET_VIS3 with
TARGET_VIS3B.
(vec_cmp): Likewise.
(fpcmpu_vis): Likewise.
(vec_cmpu): Likewise.
(vcond_mask_): Likewise.
* config/sparc/sparc.opt (VIS3B): New target mask.
* doc/invoke.texi (SPARC options): Document -mvis3b.
2025-01-18 Eric Botcazou <ebotca...@adacore.com>
* gcc.target/sparc/20230328-1.c: Pass -mvis3b instead of -mvis3.
* gcc.target/sparc/20230328-4.c: Likewise.
* gcc.target/sparc/fucmp.c: Likewise.
* gcc.target/sparc/vis3misc.c: Likewise.
--
Eric Botcazoudiff --git a/gcc/config/sparc/sparc-c.cc b/gcc/config/sparc/sparc-c.cc
index 47a22d583b6..d365da3a10b 100644
--- a/gcc/config/sparc/sparc-c.cc
+++ b/gcc/config/sparc/sparc-c.cc
@@ -52,6 +52,11 @@ sparc_target_macros (void)
cpp_define (parse_in, "__VIS__=0x400");
cpp_define (parse_in, "__VIS=0x400");
}
+ else if (TARGET_VIS3B)
+ {
+ cpp_define (parse_in, "__VIS__=0x310");
+ cpp_define (parse_in, "__VIS=0x310");
+ }
else if (TARGET_VIS3)
{
cpp_define (parse_in, "__VIS__=0x300");
diff --git a/gcc/config/sparc/sparc.cc b/gcc/config/sparc/sparc.cc
index a62b8033954..2196a0c4498 100644
--- a/gcc/config/sparc/sparc.cc
+++ b/gcc/config/sparc/sparc.cc
@@ -1671,6 +1671,8 @@ dump_target_flag_bits (const int flags)
fprintf (stderr, "VIS2 ");
if (flags & MASK_VIS3)
fprintf (stderr, "VIS3 ");
+ if (flags & MASK_VIS3B)
+ fprintf (stderr, "VIS3B ");
if (flags & MASK_VIS4)
fprintf (stderr, "VIS4 ");
if (flags & MASK_VIS4B)
@@ -1919,19 +1921,23 @@ sparc_option_override (void)
if (TARGET_VIS3)
target_flags |= MASK_VIS2 | MASK_VIS;
- /* -mvis4 implies -mvis3, -mvis2 and -mvis. */
- if (TARGET_VIS4)
+ /* -mvis3b implies -mvis3, -mvis2 and -mvis. */
+ if (TARGET_VIS3B)
target_flags |= MASK_VIS3 | MASK_VIS2 | MASK_VIS;
- /* -mvis4b implies -mvis4, -mvis3, -mvis2 and -mvis */
+ /* -mvis4 implies -mvis3b, -mvis3, -mvis2 and -mvis. */
+ if (TARGET_VIS4)
+ target_flags |= MASK_VIS3B | MASK_VIS3 | MASK_VIS2 | MASK_VIS;
+
+ /* -mvis4b implies -mvis4, -mvis3b, -mvis3, -mvis2 and -mvis */
if (TARGET_VIS4B)
- target_flags |= MASK_VIS4 | MASK_VIS3 | MASK_VIS2 | MASK_VIS;
+ target_flags |= MASK_VIS4 | MASK_VIS3B | MASK_VIS3 | MASK_VIS2 | MASK_VIS;
- /* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b, -mfmaf and -mfsmuld if
- FPU is disabled. */
+ /* Don't allow -mvis, -mvis2, -mvis3, -mvis3b, -mvis4, -mvis4b, -mfmaf and
+ -mfsmuld if FPU is disabled. */
if (!TARGET_FPU)
- target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_VIS4
- | MASK_VIS4B | MASK_FMAF | MASK_FSMULD);
+ target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_VIS3B
+ | MASK_VIS4 | MASK_VIS4B | MASK_FMAF | MASK_FSMULD);
/* -mvis assumes UltraSPARC+, so we are sure v9 instructions
are available; -m64 also implies v9. */
@@ -11451,10 +11457,6 @@ sparc_vis_init_builtins (void)
def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis,
SPARC_BUILTIN_FMEAN16, v4hi_ftype_v4hi_v4hi);
- def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis,
- SPARC_BUILTIN_FPADD64, di_ftype_di_di);
- def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis,
- SPARC_BUILTIN_FPSUB64, di_ftype_di_di);
def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3,
SPARC_BUILTIN_FPADDS16, v4hi_ftype_v4hi_v4hi);
@@ -11473,6 +11475,34 @@ sparc_vis_init_builtins (void)
def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3,
SPARC_BUILTIN_FPSUBS32S, v1si_ftype_v1si_v1si);
+ def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis,
+ SPARC_BUILTIN_FHADDS, sf_ftype_sf_sf);
+ def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis,
+ SPARC_BUILTIN_FHADDD, df_ftype_df_df);
+ def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis,
+ SPARC_BUILTIN_FHSUBS, sf_ftype_sf_sf);
+ def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis,
+ SPARC_BUILTIN_FHSUBD, df_ftype_df_df);
+ def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis,
+ SPARC_BUILTIN_FNHADDS, sf_ftype_sf_sf);
+ def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis,
+ SPARC_BUILTIN_FNHADDD, df_ftype_df_df);
+
+ def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis,
+ SPARC_BUILTIN_UMULXHI, di_ftype_di_di);
+ def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis,
+ SPARC_BUILTIN_XMULX, di_ftype_di_di);
+ def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis,
+ SPARC_BUILTIN_XMULXHI, di_ftype_di_di);
+ }
+
+ if (TARGET_VIS3B)
+ {
+ def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis,
+ SPARC_BUILTIN_FPADD64, di_ftype_di_di);
+ def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis,
+ SPARC_BUILTIN_FPSUB64, di_ftype_di_di);
+
if (TARGET_ARCH64)
{
def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fpcmpule8di_vis,
@@ -11495,26 +11525,6 @@ sparc_vis_init_builtins (void)
def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fpcmpeq8si_vis,
SPARC_BUILTIN_FUCMPEQ8, si_ftype_v8qi_v8qi);
}
-
- def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis,
- SPARC_BUILTIN_FHADDS, sf_ftype_sf_sf);
- def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis,
- SPARC_BUILTIN_FHADDD, df_ftype_df_df);
- def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis,
- SPARC_BUILTIN_FHSUBS, sf_ftype_sf_sf);
- def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis,
- SPARC_BUILTIN_FHSUBD, df_ftype_df_df);
- def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis,
- SPARC_BUILTIN_FNHADDS, sf_ftype_sf_sf);
- def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis,
- SPARC_BUILTIN_FNHADDD, df_ftype_df_df);
-
- def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis,
- SPARC_BUILTIN_UMULXHI, di_ftype_di_di);
- def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis,
- SPARC_BUILTIN_XMULX, di_ftype_di_di);
- def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis,
- SPARC_BUILTIN_XMULXHI, di_ftype_di_di);
}
if (TARGET_VIS4)
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 6db019a8a9f..4d46cfd0fb2 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -8993,7 +8993,7 @@
(match_operand:FPCMP 2 "register_operand" "e")))]
"TARGET_VIS
&& (<FPCMP:MODE>mode != V8QImode
- || (TARGET_VIS3 && (<fpcmpcond:CODE> == EQ || <fpcmpcond:CODE> == NE))
+ || (TARGET_VIS3B && (<fpcmpcond:CODE> == EQ || <fpcmpcond:CODE> == NE))
|| TARGET_VIS4)"
"fpcmp<fpcmpcond:code><FPCMP:vbits>\t%1, %2, %0"
[(set_attr "type" "viscmp")])
@@ -9003,7 +9003,7 @@
(match_operator:P 1 "vec_cmp_operator"
[(match_operand:FPCMP 2 "register_operand" "")
(match_operand:FPCMP 3 "register_operand" "")]))]
- "TARGET_VIS3"
+ "TARGET_VIS3B"
{
enum rtx_code code = GET_CODE (operands[1]);
@@ -9018,7 +9018,7 @@
[(set (match_operand:P 0 "register_operand" "=r")
(fpcmpucond:P (match_operand:FPCMP 1 "register_operand" "e")
(match_operand:FPCMP 2 "register_operand" "e")))]
- "TARGET_VIS3 && (<FPCMP:MODE>mode == V8QImode || TARGET_VIS4)"
+ "TARGET_VIS3B && (<FPCMP:MODE>mode == V8QImode || TARGET_VIS4)"
"fpcmpu<fpcmpucond:signed_code><FPCMP:vbits>\t%1, %2, %0"
[(set_attr "type" "viscmp")])
@@ -9027,7 +9027,7 @@
(match_operator:P 1 "vec_cmpu_operator"
[(match_operand:FPCMP 2 "register_operand" "")
(match_operand:FPCMP 3 "register_operand" "")]))]
- "TARGET_VIS3"
+ "TARGET_VIS3B"
{
enum rtx_code code = GET_CODE (operands[1]);
@@ -9043,7 +9043,7 @@
(match_operand:FPCMP 1 "register_operand" "")
(match_operand:FPCMP 2 "register_operand" "")
(match_operand:P 3 "register_operand" "")]
- "TARGET_VIS3"
+ "TARGET_VIS3B"
{
sparc_expand_vcond_mask (<FPCMP:MODE>mode, operands, UNSPEC_CMASK<vbits>);
DONE;
@@ -9268,7 +9268,7 @@
[(set (match_operand:V1DI 0 "register_operand" "=e")
(plusminus:V1DI (match_operand:V1DI 1 "register_operand" "e")
(match_operand:V1DI 2 "register_operand" "e")))]
- "TARGET_VIS3"
+ "TARGET_VIS3B"
"fp<plusminus_insn>64\t%1, %2, %0"
[(set_attr "type" "fga")
(set_attr "subtype" "addsub64")])
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index b635ba54a9c..2af18bf8d86 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -73,13 +73,17 @@ mvis3
Target Mask(VIS3)
Use UltraSPARC Visual Instruction Set version 3.0 extensions.
+mvis3b
+Target Mask(VIS3B)
+Use additional VIS 3 instructions introduced in OSA2011.
+
mvis4
Target Mask(VIS4)
Use UltraSPARC Visual Instruction Set version 4.0 extensions.
mvis4b
Target Mask(VIS4B)
-Use additional VIS instructions introduced in OSA2017.
+Use additional VIS 4 instructions introduced in OSA2017.
mcbcond
Target Mask(CBCOND)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index dd0d2b41a1a..9764678f8c0 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1412,7 +1412,8 @@ See RS/6000 and PowerPC Options.
-munaligned-doubles -mno-unaligned-doubles
-muser-mode -mno-user-mode
-mv8plus -mno-v8plus -mvis -mno-vis
--mvis2 -mno-vis2 -mvis3 -mno-vis3
+-mvis2 -mno-vis2
+-mvis3 -mno-vis3 -mvis3b -mno-vis3b
-mvis4 -mno-vis4 -mvis4b -mno-vis4b
-mcbcond -mno-cbcond -mfmaf -mno-fmaf -mfsmuld -mno-fsmuld
-mpopc -mno-popc -msubxc -mno-subxc
@@ -33841,6 +33842,18 @@ default is @option{-mvis3} when targeting a cpu that supports such
instructions, such as niagara-3 and later. Setting @option{-mvis3}
also sets @option{-mvis2} and @option{-mvis}.
+@opindex mvis3b
+@opindex mno-vis3b
+@item -mvis3b
+@itemx -mno-vis3b
+With @option{-mvis3b}, GCC generates code that takes advantage of
+version 3.0 of the UltraSPARC Visual Instruction Set extensions, plus
+the additional VIS instructions introduced in the Oracle SPARC
+Architecture 2011. The default is @option{-mvis3b} when targeting
+a cpu that supports such instructions, such as niagara-7 and later.
+Setting @option{-mvis3b} also sets @option{-mvis3}, @option{-mvis2}
+and @option{-mvis}.
+
@opindex mvis4
@opindex mno-vis4
@item -mvis4
@@ -33849,7 +33862,8 @@ With @option{-mvis4}, GCC generates code that takes advantage of
version 4.0 of the UltraSPARC Visual Instruction Set extensions. The
default is @option{-mvis4} when targeting a cpu that supports such
instructions, such as niagara-7 and later. Setting @option{-mvis4}
-also sets @option{-mvis3}, @option{-mvis2} and @option{-mvis}.
+also sets @option{-mvis3b}, @option{-mvis3}, @option{-mvis2} and
+@option{-mvis}.
@opindex mvis4b
@opindex mno-vis4b
@@ -33860,8 +33874,8 @@ version 4.0 of the UltraSPARC Visual Instruction Set extensions, plus
the additional VIS instructions introduced in the Oracle SPARC
Architecture 2017. The default is @option{-mvis4b} when targeting a
cpu that supports such instructions, such as m8 and later. Setting
-@option{-mvis4b} also sets @option{-mvis4}, @option{-mvis3},
-@option{-mvis2} and @option{-mvis}.
+@option{-mvis4b} also sets @option{-mvis4}, @option{-mvis3b},
+@option{-mvis3}, @option{-mvis2} and @option{-mvis}.
@opindex mcbcond
@opindex mno-cbcond
diff --git a/gcc/testsuite/gcc.target/sparc/20230328-1.c b/gcc/testsuite/gcc.target/sparc/20230328-1.c
index 49acf0b5d58..632d27d08b2 100644
--- a/gcc/testsuite/gcc.target/sparc/20230328-1.c
+++ b/gcc/testsuite/gcc.target/sparc/20230328-1.c
@@ -1,6 +1,6 @@
/* PR target/109140 */
/* { dg-do compile } */
-/* { dg-options "-O3 -mvis3 -std=c99" } */
+/* { dg-options "-O3 -mvis3b -std=c99" } */
#define TYPE unsigned char
diff --git a/gcc/testsuite/gcc.target/sparc/20230328-4.c b/gcc/testsuite/gcc.target/sparc/20230328-4.c
index d51eb06b9d0..4e4632bea2a 100644
--- a/gcc/testsuite/gcc.target/sparc/20230328-4.c
+++ b/gcc/testsuite/gcc.target/sparc/20230328-4.c
@@ -1,6 +1,6 @@
/* PR target/109140 */
/* { dg-do compile } */
-/* { dg-options "-O3 -mvis3 -std=c99" } */
+/* { dg-options "-O3 -mvis3b -std=c99" } */
#define TYPE short
diff --git a/gcc/testsuite/gcc.target/sparc/fucmp.c b/gcc/testsuite/gcc.target/sparc/fucmp.c
index c4542806e34..e4bd91626a4 100644
--- a/gcc/testsuite/gcc.target/sparc/fucmp.c
+++ b/gcc/testsuite/gcc.target/sparc/fucmp.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mvis3" } */
+/* { dg-options "-mvis3b" } */
typedef unsigned char vec8 __attribute__((vector_size(8)));
diff --git a/gcc/testsuite/gcc.target/sparc/vis3misc.c b/gcc/testsuite/gcc.target/sparc/vis3misc.c
index 7286d705dd5..3868314ad97 100644
--- a/gcc/testsuite/gcc.target/sparc/vis3misc.c
+++ b/gcc/testsuite/gcc.target/sparc/vis3misc.c
@@ -1,5 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-mvis3" } */
+/* { dg-options "-mvis3b" } */
+
typedef int __v2si __attribute__((vector_size(8)));
typedef short __v4hi __attribute__((vector_size(8)));
typedef unsigned char __v8qi __attribute__((vector_size(8)));
