Sorry for the slow response. Xi Ruoyao <xry...@xry111.site> writes: > Hi Richard, > > When I hack the LoongArch backend I notice something like > > slli.d $r4, $r4, 2 > add.w $r4, $r4, $r5 > > Or > > (set (reg:DI 4) (ashift:DI (reg:DI 4) (const_int 2)) > (set (reg:DI 4) > (sign_extend:DI (add:SI (reg:SI 4) (reg:SI 5)))) > > can appear after split. On LoongArch it can be done via an alsl.w > instruction, so I attempted to combine them in late combine with: > > (define_insn > [(set (match_operand:DI 0 "register_operand" "=r") > (sign_extend:DI > (add:SI > (subreg:SI > (ashift:DI (match_operand:DI 1 "register_operand" "r") > (match_operand:SI 2 "const_immalsl_operand" "")) > 0) > (match_operand:SI 3 "register_operand" "r"))))] > "TARGET_64BIT" > "alsl.w\t%0,%1,%3,%2") > > But this does not work and I get "RTL substitution failed" with > -fdump-rtl-late_combine2-details. > > I want to open an RFE in Bugzilla. But before that I'm wondering: maybe > I'm just too stupid to figure out the correct way for this?
At the moment, insn_propagation::apply_to_rvalue_1 chickens out of a change in hard register mode that would involve an explicit subreg. In this particular case, I'd hope that the subreg:SI would be pushed into the ashift to give an ashift:SI of a reg:SI, but it seems that that isn't happening for some reason. It probably has something to do with WORD_REGISTER_OPERATIONS (which loongson defines, but aarch64 doesn't). That answer only applies to some codes though. Shifts right would still hit the problem you mention. I think it'd be ok to try to relax the condition if a port needs it -- the current code is (supposed to be) deliberately conservative. Thanks, Richard
