On Tue, Jun 4, 2024 at 8:52 AM Stefan Schulze Frielinghaus via Gcc <gcc@gcc.gnu.org> wrote: > > Hi all, > > Is there some sort of guarantee that the unused part of a partial vector has > all bits set to zero? > > The question came up while implementing an insn for mode V2SF on s390 > where only half of the hard register would be utilized. The final > machine instruction, however, would make use of the full register > (V4SF). Therefore, if the other half is not guaranteed to be zero, then > a floating-point exception might occur in this particular case. Of > course, if such a guarantee exists, then one would have to maintain that > for all insn implementations. > > This all sounds a bit fragile and probably better solved by having some > sort of masking support by the hardware but I'm still keen to know.
There is no guarantee by the middle-end (like having PROMOTE_MODE for vectors). You may want to look how x86 implements MMX-with-SSE (aka 8 byte vectors within 16 byte SSE regs). In particular there's no generic middle-end support for "lowering" V2SFmode to V4SFmode during RTL expansion, your machine description expanders have to do that. Richard. > Cheers, > Stefan
