Kaz Kojima wrote:
some compile time errors in c/c++ test for sh64-unknown-linux-elf
http://gcc.gnu.org/ml/gcc-testresults/2005-09/msg00466.html
3 tests
gcc.c-torture/compile/simd-4.c
gcc.c-torture/execute/20050604-1.c
gcc.dg/torture/pr21817-1.c
fail with the similar ICE:
gcc/gcc/testsuite/gcc.c-torture/compile/simd-4.c: In function 'tempf':
gcc/gcc/testsuite/gcc.c-torture/compile/simd-4.c:15: error: unable to find a
register to spill in class 'GENERAL_REGS'
gcc/gcc/testsuite/gcc.c-torture/compile/simd-4.c:15: error: this is the insn:
(insn 53 52 54 0 (set (subreg:DI (reg:V4SF 68 fr4 [196]) 0)
(and:DI (subreg:DI (reg:V4SF 68 fr4 [196]) 0)
(const_int -4294967296 [0xffffffff00000000]))) 85 {anddi3} (nil)
(nil))
Yes, these appeared also in the simulator tests.
It seems odd that the DImode subregs of V4SFmode registers are used
as the operands of logical operations, though I don't understand why
reload complains as above.
reload complained because HARD_REGNO_MODE_OK disallowed
V4SFmode in GENERAL_REGS. Allowing that also causes register
allocation to use GENERAL_REGS in the first place. An and with a
J16 constraint can also be done with FP_REGS using mov.ls from r63.
A natural way to implement this would use an fr (or rf) constraint in
one of the alternatives. While looking at this I also found that we were
missing a register class for an fr constraint. I've tested the attached
patch over the weekend for sh-elf and sh64-elf, and checked it in now.
2005-09-12 J"orn Rennecke <[EMAIL PROTECTED]>
* sh.h (HARD_REGNO_MODE_OK): Allow V4SFmode in general purpose
registers for TARGET_SHMEDIA.
(enum reg_class, REG_CLASS_NAMES, REG_CLASS_CONTENTS): Rename
GENERAL_FP_REGS to GENERAL_DF_REGS. Add GENERAL_FP_REGS as union
of GENERAL_REGS and FP_REGS.
Index: sh.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.h,v
retrieving revision 1.276
diff -p -r1.276 sh.h
*** sh.h 6 Aug 2005 13:26:24 -0000 1.276
--- sh.h 12 Sep 2005 13:21:53 -0000
*************** extern char sh_additional_register_names
*** 1152,1158 ****
|| GENERAL_REGISTER_P (REGNO)) \
: (MODE) == V4SFmode \
? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
! || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
: (MODE) == V16SFmode \
? (TARGET_SHMEDIA \
? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
--- 1152,1158 ----
|| GENERAL_REGISTER_P (REGNO)) \
: (MODE) == V4SFmode \
? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
! || GENERAL_REGISTER_P (REGNO)) \
: (MODE) == V16SFmode \
? (TARGET_SHMEDIA \
? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
*************** enum reg_class
*** 1341,1346 ****
--- 1341,1347 ----
DF_REGS,
FPSCR_REGS,
GENERAL_FP_REGS,
+ GENERAL_DF_REGS,
TARGET_REGS,
ALL_REGS,
LIM_REG_CLASSES
*************** enum reg_class
*** 1365,1370 ****
--- 1366,1372 ----
"DF_REGS", \
"FPSCR_REGS", \
"GENERAL_FP_REGS", \
+ "GENERAL_DF_REGS", \
"TARGET_REGS", \
"ALL_REGS", \
}
*************** enum reg_class
*** 1402,1408 ****
/* FPSCR_REGS: */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
/* GENERAL_FP_REGS: */
\
! { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
/* TARGET_REGS: */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
/* ALL_REGS: */ \
--- 1404,1412 ----
/* FPSCR_REGS: */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
/* GENERAL_FP_REGS: */
\
! { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
! /* GENERAL_DF_REGS: */
\
! { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
/* TARGET_REGS: */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
/* ALL_REGS: */ \
