Thank you for so much help.
Now I can successfully combine a arith instrucion & compare.
But another problem occurs, that is our RISC machine has
logical instructions which only update the Zero flag.
Thus only eq & neq branch can be combined with.
For example
case 1 (can combine)
or_c dst, sr1, sr2 <-- update Z
beq <-- use Z only
case 2 (can not combine)
or_c dst, sr1, sr2
compare dst, 0 <-- another compare is needed
ble <-- use Z & N & V
I use a CC_Zmode to describe this.
My pattern is:
[(set (reg:CC_Z CC_REGNUM)
(compare:CC_Z
(ior:SI [(match_operand:SI 1 "register_operand" "g")
(match_operand:SI 2 "register_operand"
"g")])
(const_int 0)))
(set (match_operand:SI 0 "register_operand" "=g")
(ior:SI [(match_dup 1) (match_dup 2)]))])]
Use gdb to trace the cc1 I saw
step1) cmpsi is invoked
(define_expand "cmpsi"
[(match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "arith_operand" "")]
""
{
compare_op0 = operands[0];
compare_op1 = operands[1];
}
step2)
(define_expand "beq"
[(set (pc)
(if_then_else (eq (match_dup 1) (const_int 0))
(label_ref (match_operand 0 "" ""))
(pc)))]
""
{
enum machine_mode mode = SELECT_CC_MODE(EQ, cmp_op0, cmp_op1);
/*
Because cmp_op0 is pseudo register, mode is always
the CCmode
*/
rtx cc_reg = gen_rtx_REG(mode, CC_REGNUM);
emit_insn(gen_rtx_SET(VOIDmode, cc_reg,
gen_rtx_COMPARE(mode, cmp_op0, cmp_op1)));
/*
generate (set (reg:CC 33 ) (compare:CC (ior...)))
*/
operands[1] = cc_reg;
}
)
step3) select_cc_mode()
I set a break point in select_cc_mode() and found
it is invoked several times.
score_select_cc_mode(enum rtx_code op, rtx x, rtx y){
if( GET_MODE(x) == SImode && GET_CODE(x) == IOR){
if(op == NE || op == EQ)
return CC_Zmode;
else
return CCmode;
}
...
}
I also saw a
(set (reg:CC 33 ) (compare:CC (ior...)))
is changed to
(set (reg:CC_Z 33 ) (compare:CC_Z (ior...)))
Unfortunately, the combination still failed.
The rtl pattern(*.29.ce3) is
(insn:HI 10 9 11 0 main.c:71
(set (reg:CC_Z 33 cr1)
(compare:CC_Z
(ior:SI (reg:SI 4 r4 [ a ]) (const_int 16
[0x10]))
(const_int 0 [0x0])))
(set (reg:SI 4 r4 [168])
(ior:SI (reg:SI 4 r4 [ a ]) (const_int 16 [0x10]))))
]) 8 {bitset} (nil)
(expr_list:REG_UNUSED (reg:CC_Z 33 cr1)
(nil)))
(insn:HI 11 10 12 0 main.c:71 (set (reg:CC 33 cr1)
(compare:CC (reg:SI 4 r4 [168])
(const_int 0 [0x0]))) 42 {cmpsi_internal} (insn_list 10 (nil))
(expr_list:REG_DEAD (reg:SI 4 r4 [168])
(nil)))
I also trace the implementation of arm.
But it also generate a compare instruction even there is
a possibility to combine it with previous arith instructions.
I've spent so much time on it.
Can any one help me ?
