Jon,
How is the latency of instructions that have side effects modeled in the DFA
scheduler. For example, define_insn_reservation only has one latency value,
yet instructions such as loads with post increment addressing have two
outputs, possibly with different latencies. Do both outputs get the same
latency?
you should set the latency to the larger of those two values. You can then
insert bypasses for the shorter one. Look at the arm schedulers, which
have instances of that going on.
nathan
--
Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery LLC
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