> From: Marek Michalkiewicz <[EMAIL PROTECTED]> >> - Fully agree, just can't keep from wondering if this may be most >> efficiency accomplish by simply requiring the alignment of all >> function entry points to be two instruction word aligned. Thereby > > This only doubles the available address space, and I'd rather not do > it all again (this time with 4-word alignment) if 512K chips appear.
- understood, however unlikely; observing it will likely take Atmel at least 2-3 years to stabilize production of the 256K devices, and larger device volume potential vs. competitive offerings couldn't likely justify their development (as just an opinion). > But function entry points are not the only problem - indirect jumps are > another (as you can see in the subject of my message), they can point > somewhere within a function (so function alignment may not help here). > On the other hand, indirect_jump is rarely seen, so it must be correct > but doesn't have to be very efficient (OK if it costs even a few more > instructions to stay in the low 64K words). - Sorry, I'm confused; can you give me an example of legal C expression specifying an indirect jump to an arbitrary location within a function? (as unless I misunderstand, there's no such thing?) I suspect they only exist as a result of a possible switch statement optimization strategy, which should have nothing to do with the size of the target's data pointers, therefore likely stored and accessed however convenient by the compiler in program memory (not data memory) independently of the representation chosen for function-pointers. (I'd guess) > So, I'm trying to figure out when the indirect_jump pattern can actually > be generated on the AVR (haven't yet seen it in any real application), > and where does the pointer comes from (to see if the jump target can be > moved to the low 64K words somehow). > > Marek
