On 2014-12-17 7:59 PM, Kaz Kojima wrote:
This was discussed in PR55212
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c52
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c53
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c55
and is to fix ICE in assign_by_spills.
In that case, rtlanal.c:decompose_mem_address guesses base and index
regs when INDEX_REG_CLASS is assigned to that base candidate already.
This will be OK for almost targets but is bad for SH which has only
one register r0 in INDEX_REG_CLASS. The patch fix-ups it with
swapping these candidates.
--
* lra-constraints.c (process_address_1): Swap base_term and
index_term if INDEX_REG_CLASS is assigned to base_term already
when INDEX_REG_CLASS is a single register class.
The patch is ok. Although I will probably try to generalize it in future.
Thanks, again.
