This was discussed in PR55212 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c52 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c53 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=55212#c55
and is to fix ICE in assign_by_spills. In that case, rtlanal.c:decompose_mem_address guesses base and index regs when INDEX_REG_CLASS is assigned to that base candidate already. This will be OK for almost targets but is bad for SH which has only one register r0 in INDEX_REG_CLASS. The patch fix-ups it with swapping these candidates. -- * lra-constraints.c (process_address_1): Swap base_term and index_term if INDEX_REG_CLASS is assigned to base_term already when INDEX_REG_CLASS is a single register class. diff --git a/lra-constraints.c b/lra-constraints.c index a67bf8a..47cbbec 100644 --- a/lra-constraints.c +++ b/lra-constraints.c @@ -2828,6 +2828,20 @@ process_address_1 (int nop, bool check_only_p, decompose_mem_address (&ad, SUBREG_REG (op)); else return false; + /* If INDEX_REG_CLASS is assigned to base_term already and isn't to + index_term, swap them so to avoid assigning INDEX_REG_CLASS to both + when INDEX_REG_CLASS is a single register class. */ + if (ad.base_term != NULL + && ad.index_term != NULL + && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 + && REG_P (*ad.base_term) + && REG_P (*ad.index_term) + && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) + && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) + { + std::swap (ad.base, ad.index); + std::swap (ad.base_term, ad.index_term); + } if (! check_only_p) change_p = equiv_address_substitution (&ad); if (ad.base_term != NULL