>What happens when shift == 16? We emit just gen_avx2_permv2ti. We don't need additional palignr.
On Tue, Sep 30, 2014 at 9:06 PM, Uros Bizjak <ubiz...@gmail.com> wrote: > On Tue, Sep 30, 2014 at 6:47 PM, Evgeny Stupachenko <evstu...@gmail.com> > wrote: > >> Patch resubmitted from >> https://gcc.gnu.org/ml/gcc-patches/2014-09/msg01400.html >> >> The patch fix PR62128 and "gcc.target/i386/pr52252-atom.c" in >> core-avx2 make check. >> The test in pr62128 is exactly TEST 22 from >> gcc.dg/torture/vshuf-v32qi.c. It will check if the pattern is correct >> or not. >> The patch developed similar to define_insn_and_split >> "*avx_vperm_broadcast_<mode>". >> The patch passed x86 bootstrap and make check (+2 new passes for >> -march=core-avx2). >> Is it ok? >> >> Evgeny >> >> ChangeLog: >> >> 2014-09-30 Evgeny Stupachenko <evstu...@gmail.com> >> >> * config/i386/sse.md (avx2_palignrv4di): New. >> * config/i386/sse.md (avx2_rotate<mode>_perm): New. > > +(define_insn "avx2_palignrv4di" > + [(set (match_operand:V4DI 0 "register_operand" "=x") > + (unspec:V4DI > + [(match_operand:V4DI 1 "register_operand" "x") > + (match_operand:V4DI 2 "nonimmediate_operand" "xm") > + (match_operand:SI 3 "const_0_to_255_operand" "n")] > + UNSPEC_VPALIGNRDI))] > + "TARGET_AVX2" > + "vpalignr\t{%3, %2, %1, %0|%0, %1, %2, %3}" > + [(set_attr "type" "sselog") > + (set_attr "prefix" "vex") > + (set_attr "mode" "OI")]) > > Just reuse UNSPEC_PALIGNR, no need for a new unspec. > > +(define_insn_and_split "avx2_rotate<mode>_perm" > + [(set (match_operand:V_256 0 "register_operand" "=&x") > + (vec_select:V_256 > + (match_operand:V_256 1 "register_operand" "x") > + (match_parallel 2 "palignr_operand" > + [(match_operand 3 "const_int_operand" "n")])))] > + "TARGET_AVX2" > + "#" > + "&& reload_completed" > + [(const_int 0)] > > This should be a define_expand. There is nothing that requires hard > registers. You can achieve mode-changes by using gen_lowpart, see many > examples in sse.md > > + if (shift < 16) > + emit_insn (gen_avx2_palignrv4di (op0, > + op0, > + op1, > + GEN_INT (shift))); > + else if (shift > 16) > + emit_insn (gen_avx2_palignrv4di (op0, > + op1, > + op0, > + GEN_INT (shift - 16))); > > What happens when shift == 16? > > Uros.
