On 06/03/2014 12:56 PM, Kai Tietz wrote: > +(define_insn "*sibcall_intern" > + [(call (unspec [(mem:QI (match_operand:W 0 "memory_operand"))] > UNSPEC_PEEPSIB) > + (match_operand 1))] > + "" > + "* SIBLING_CALL_P (insn) = 1; return ix86_output_call_insn (insn, > operands[0]);" > + [(set_attr "type" "call")])
Why would this be hard to do when first emitting it? > +; TODO > +(define_peephole2 > + [(set (match_operand:DI 0 "register_operand") > + (match_operand:DI 1 "memory_operand")) > + (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] > + "TARGET_64BIT" > + [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) > + (set (match_dup 0) > + (match_dup 1))]) > + > +(define_peephole2 > + [(set (match_operand:SI 0 "register_operand") > + (match_operand:SI 1 "memory_operand")) > + (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] > + "!TARGET_64BIT" > + [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) > + (set (match_dup 0) > + (match_dup 1))]) These are wrong. This allows unrestricted movement across the blockage. > +(define_peephole2 > + [(set (match_operand:DI 0 "register_operand") > + (match_operand:DI 1 "memory_operand")) > + (call (mem:QI (match_operand:DI 2 "register_operand")) > + (match_operand 3))] > + "TARGET_64BIT && REG_P (operands[0]) > + && REG_P (operands[2]) > + && SIBLING_CALL_P (peep2_next_insn (1)) > + && REGNO (operands[0]) == REGNO (operands[2])" > + [(call (unspec [(mem:QI (match_dup 1))] UNSPEC_PEEPSIB) (match_dup 3))]) What you wanted was to match 3 insns in a peephole like this, including the blockage, and including re-emitting the blockage in the output. r~
