On Thu, Mar 27, 2014 at 10:53 AM, Alan Lawrence <alan.lawre...@arm.com> wrote: > Final patch adds new tests of the ARM ZIP Intrinsics (subsuming the > autogenerated ones in testsuite/gcc.target/arm/neon/), that also check the > execution results, reusing the test bodies introduced into AArch64 in the > first patch. > > All tests passing on arm-none-eabi.
This is OK - thanks, Ramana > > gcc/testsuite/ChangeLog: > 2012-03-27 Alan Lawrence <alan.lawre...@arm.com> > > * gcc.target/arm/simd/simd.exp: New file. > * gcc.target/arm/simd/vzipqf32_1.c: New file. > * gcc.target/arm/simd/vzipqp16_1.c: New file. > * gcc.target/arm/simd/vzipqp8_1.c: New file. > * gcc.target/arm/simd/vzipqs16_1.c: New file. > * gcc.target/arm/simd/vzipqs32_1.c: New file. > * gcc.target/arm/simd/vzipqs8_1.c: New file. > * gcc.target/arm/simd/vzipqu16_1.c: New file. > * gcc.target/arm/simd/vzipqu32_1.c: New file. > * gcc.target/arm/simd/vzipqu8_1.c: New file. > * gcc.target/arm/simd/vzipf32_1.c: New file. > * gcc.target/arm/simd/vzipp16_1.c: New file. > * gcc.target/arm/simd/vzipp8_1.c: New file. > * gcc.target/arm/simd/vzips16_1.c: New file. > * gcc.target/arm/simd/vzips32_1.c: New file. > * gcc.target/arm/simd/vzips8_1.c: New file. > * gcc.target/arm/simd/vzipu16_1.c: New file. > * gcc.target/arm/simd/vzipu32_1.c: New file. > * gcc.target/arm/simd/vzipu8_1.c: New file. > diff --git a/gcc/testsuite/gcc.target/arm/simd/simd.exp > b/gcc/testsuite/gcc.target/arm/simd/simd.exp > new file mode 100644 > index 0000000..746429d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/simd.exp > @@ -0,0 +1,35 @@ > +# Copyright (C) 1997-2014 Free Software Foundation, Inc. > + > +# This program is free software; you can redistribute it and/or modify > +# it under the terms of the GNU General Public License as published by > +# the Free Software Foundation; either version 3 of the License, or > +# (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with GCC; see the file COPYING3. If not see > +# <http://www.gnu.org/licenses/>. > + > +# GCC testsuite that uses the `dg.exp' driver. > + > +# Exit immediately if this isn't an ARM target. > +if ![istarget arm*-*-*] then { > + return > +} > + > +# Load support procs. > +load_lib gcc-dg.exp > + > +# Initialize `dg'. > +dg-init > + > +# Main loop. > +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \ > + "" "" > + > +# All done. > +dg-finish > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c > new file mode 100644 > index 0000000..efaa96e > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipf32' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipf32.x" > + > +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, > ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c > new file mode 100644 > index 0000000..4154333 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipp16' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipp16.x" > + > +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[dD\]\[0-9\]+, > ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c > new file mode 100644 > index 0000000..9fe2384 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipp8' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipp8.x" > + > +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[dD\]\[0-9\]+, > ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c > new file mode 100644 > index 0000000..8c547a7 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipQf32' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipqf32.x" > + > +/* { dg-final { scan-assembler-times "vzip\.32\[ \t\]+\[qQ\]\[0-9\]+, > ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c > new file mode 100644 > index 0000000..e2af10b > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipQp16' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipqp16.x" > + > +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[qQ\]\[0-9\]+, > ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c > new file mode 100644 > index 0000000..11a1329 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipQp8' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipqp8.x" > + > +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[qQ\]\[0-9\]+, > ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c > new file mode 100644 > index 0000000..0576c00 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipQs16' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipqs16.x" > + > +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[qQ\]\[0-9\]+, > ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c > new file mode 100644 > index 0000000..6cf2439 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipQs32' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipqs32.x" > + > +/* { dg-final { scan-assembler-times "vzip\.32\[ \t\]+\[qQ\]\[0-9\]+, > ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c > new file mode 100644 > index 0000000..0244374 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipQs8' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipqs8.x" > + > +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[qQ\]\[0-9\]+, > ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c > new file mode 100644 > index 0000000..3c406f5 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipQu16' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipqu16.x" > + > +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[qQ\]\[0-9\]+, > ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c > new file mode 100644 > index 0000000..ba1393c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipQu32' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipqu32.x" > + > +/* { dg-final { scan-assembler-times "vzip\.32\[ \t\]+\[qQ\]\[0-9\]+, > ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c > new file mode 100644 > index 0000000..023ecac > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipQu8' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipqu8.x" > + > +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[qQ\]\[0-9\]+, > ?\[qQ\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c > new file mode 100644 > index 0000000..b6c3c2f > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzips16' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzips16.x" > + > +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[dD\]\[0-9\]+, > ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c > new file mode 100644 > index 0000000..1a6f170 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzips32' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzips32.x" > + > +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, > ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c > new file mode 100644 > index 0000000..8569357 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzips8' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzips8.x" > + > +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[dD\]\[0-9\]+, > ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c > new file mode 100644 > index 0000000..23bfcc4 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipu16' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipu16.x" > + > +/* { dg-final { scan-assembler-times "vzip\.16\[ \t\]+\[dD\]\[0-9\]+, > ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c > new file mode 100644 > index 0000000..6a753f2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipu32' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipu32.x" > + > +/* { dg-final { scan-assembler-times "vuzp\.32\[ \t\]+\[dD\]\[0-9\]+, > ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */ > diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c > b/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c > new file mode 100644 > index 0000000..972af74 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c > @@ -0,0 +1,12 @@ > +/* Test the `vzipu8' ARM Neon intrinsic. */ > + > +/* { dg-do run } */ > +/* { dg-require-effective-target arm_neon_ok } */ > +/* { dg-options "-save-temps -O1 -fno-inline" } */ > +/* { dg-add-options arm_neon } */ > + > +#include "arm_neon.h" > +#include "../../aarch64/simd/vzipu8.x" > + > +/* { dg-final { scan-assembler-times "vzip\.8\[ \t\]+\[dD\]\[0-9\]+, > ?\[dD\]\[0-9\]+!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */ > +/* { dg-final { cleanup-saved-temps } } */
