On Thu, Feb 20, 2014 at 4:39 PM, Ilya Tocar <tocarip.in...@gmail.com> wrote:
> Latest version of AVX512 spec > http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf > Has a few changes. > This patch fixes first of them: > Vptestnmd and vptestnmq instructions now have CPUID AVX512F instead of > AVX512CD. This path changes thier CPUID accordingly. > However I have a question about other changes: > > 1)PREFETCHWT1 instruction now has separate CPUID bit PREFETCHWT1. > We can either support new CPUID or disable PREFETCHWT1 from generating, > without removing code, and enable it in 4.9.1/latest version. > I am not sure that adding new -m flag and related stuff this late > is a good idea. Should still add it? Please submit the patch anyway. We can relax release constraints on non-algorithmic patch a bit, weighting in benefits of having gcc release that fully conforms to some published specification. > 2)Currently for scatter/gather prefetches intrinsics we accept 1 as > possible hint parameter. This is consistent with ICC. However as > GCC defines _MM_HINT_T0 to 3 and not to 1 as ICC > (see http://gcc.gnu.org/bugzilla/show_bug.cgi?id=56603), gather prefethces > are inconsistent with normal prefetches as they won't accept _MM_HINT_T0 as > hint. We can either change gather prefetches to accept 1 instead of 3 and > hope that everyone will use _MM_HINT_T0 and not the raw value, or we can > change _MM_HINT_T0 to be consistent with ICC. What solution do you > prefer? Builtins, including __builtin_prefetch, are considered as internal implementation detail, so we can pass to them wharever we like. The published interface is in *.h files, and this includes _MM_HINT_T0. For now, I suggest to change prefetches, so they will accept _MM_HINT_T0, as this is the least invasive change. FWIW, we can change _MM_HINT_T0 in the future, as intrinsic headers correspond to the compiler, but it will raise maintenance burden (you can't just recompile sources involving builtins with different versions of the compiler anymore due to difference in constant arguments). > Patch bellow changes CPUID of vptestnmq/vptestnmd and changes some bogus > %v to v. Bootstraps, passes make check. Ok for trunk? > > ChangeLog > > 2014-02-20 Ilya Tocar <ilya.to...@intel.com> > > * config/i386/avx512fintrin.h (_mm512_testn_epi32_mask), > (_mm512_mask_testn_epi32_mask), (_mm512_testn_epi64_mask), > (_mm512_mask_testn_epi64_mask): Move to ... > * config/i386/avx512cdintrin.h: Here. > * config/i386/i386.c (bdesc_args): Change MASK_ISA for testnm. > * config/i386/sse.md (avx512f_vmscalef<mode><round_name>): Remove %. > (avx512f_scalef<mode><mask_name><round_name>): Ditto. > (avx512f_testnm<mode>3<mask_scalar_merge_name>): Change conditon to > TARGET_AVX512F from TARGET_AVX512CD. > > And for testsuite > > 2014-02-20 Ilya Tocar <ilya.to...@intel.com> > > * gcc.target/i386/avx512cd-vptestnmd-1.c: Change into ... > * gcc.target/i386/avx512f-vptestnmd-1.c: This. > * gcc.target/i386/avx512cd-vptestnmq-1.c: Change into ... > * gcc.target/i386/avx512f-vptestnmq-1.c: This. > * gcc.target/i386/avx512cd-vptestnmd-2.c: Change into ... > * gcc.target/i386/avx512f-vptestnmd-2.c: This. > * gcc.target/i386/avx512cd-vptestnmq-2.c: Change into ... > * gcc.target/i386/avx512f-vptestnmq-2.c: This. This is OK for mainline. Thanks, Uros.
