On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich <philipp.toms...@theobroma-systems.com> wrote:
Can you add a testcase or two for this patch? Having an example will help people in the future understand why these patterns are added. Thanks, Andrew Pinski > --- > gcc/config/aarch64/aarch64.md | 56 > +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 56 insertions(+) > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 60e42af..c72d123 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -2227,6 +2227,62 @@ > [(set_attr "type" "alus_ext")] > ) > > +(define_insn "*zext<mode>qi3_compare0" > + [(set (reg:CC_ZESWP CC_REGNUM) > + (compare:CC_ZESWP > + (zero_extend:GPI (match_operand:QI 1 "register_operand" "r")) > + (const_int 0))) > + (set (match_operand:GPI 0 "register_operand" "=r") > + (zero_extend:GPI (match_dup 1)))] > + "" > + "ands\\t%<w>0, %<w>1, 0xFF" > + [(set_attr "type" "logics_imm")] > +) > + > +(define_insn "*zext<mode>hi3_compare0" > + [(set (reg:CC_ZESWP CC_REGNUM) > + (compare:CC_ZESWP > + (zero_extend:GPI (match_operand:HI 1 "register_operand" "r")) > + (const_int 0))) > + (set (match_operand:GPI 0 "register_operand" "=r") > + (zero_extend:GPI (match_dup 1)))] > + "" > + "ands\\t%<w>0, %<w>1, 0xFFFF" > + [(set_attr "type" "logics_imm")] > +) > + > +(define_insn "*zextdisi3_compare0" > + [(set (reg:CC_ZESWP CC_REGNUM) > + (compare:CC_ZESWP > + (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) > + (const_int 0))) > + (set (match_operand:DI 0 "register_operand" "=r") > + (zero_extend:DI (match_dup 1)))] > + "" > + "ands\\t%x0, %x1, 0xFFFFFFFF" > + [(set_attr "type" "logics_imm")] > +) > + > +(define_insn "*zextqi3nr_compare0" > + [(set (reg:CC_ZESWP CC_REGNUM) > + (compare:CC_ZESWP > + (match_operand:QI 0 "register_operand" "r") > + (const_int 0)))] > + "" > + "tst\\t%w0, 0xFF" > + [(set_attr "type" "logics_imm")] > +) > + > +(define_insn "*zexthi3nr_compare0" > + [(set (reg:CC_ZESWP CC_REGNUM) > + (compare:CC_ZESWP > + (match_operand:HI 0 "register_operand" "r") > + (const_int 0)))] > + "" > + "tst\\t%w0, 0xFFFF" > + [(set_attr "type" "logics_imm")] > +) > + > ;; ------------------------------------------------------------------- > ;; Store-flag and conditional select insns > ;; ------------------------------------------------------------------- > -- > 1.9.0 >
