On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich
<philipp.toms...@theobroma-systems.com> wrote:
Can you add a testcase or two for this?
Thanks,
Andrew
> ---
> gcc/config/aarch64/aarch64.md | 17 +++++++++++++++++
> gcc/config/arm/types.md | 2 ++
> 2 files changed, 19 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 99a6ac8..b972a1b 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -293,6 +293,23 @@
> [(set_attr "type" "no_insn")]
> )
>
> +(define_insn "prefetch"
> + [(prefetch (match_operand:DI 0 "register_operand" "r")
> + (match_operand:QI 1 "const_int_operand" "n")
> + (match_operand:QI 2 "const_int_operand" "n"))]
> + ""
> + "*
> +{
> + if (INTVAL(operands[2]) == 0)
> + /* no temporal locality */
> + return (INTVAL(operands[1])) ? \"prfm\\tPSTL1STRM, [%0, #0]\" :
> \"prfm\\tPLDL1STRM, [%0, #0]\";
> +
> + /* temporal locality */
> + return (INTVAL(operands[1])) ? \"prfm\\tPSTL1KEEP, [%0, #0]\" :
> \"prfm\\tPLDL1KEEP, [%0, #0]\";
> +}"
> + [(set_attr "type" "prefetch")]
> +)
> +
> (define_insn "trap"
> [(trap_if (const_int 1) (const_int 8))]
> ""
> diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
> index cc39cd1..1d1280d 100644
> --- a/gcc/config/arm/types.md
> +++ b/gcc/config/arm/types.md
> @@ -117,6 +117,7 @@
> ; mvn_shift_reg inverting move instruction, shifted operand by a
> register.
> ; no_insn an insn which does not represent an instruction in the
> ; final output, thus having no impact on scheduling.
> +; prefetch a prefetch instruction
> ; rbit reverse bits.
> ; rev reverse bytes.
> ; sdiv signed division.
> @@ -553,6 +554,7 @@
> call,\
> clz,\
> no_insn,\
> + prefetch,\
> csel,\
> crc,\
> extend,\
> --
> 1.9.0
>
