On Tue, Feb 18, 2014 at 1:09 PM, Philipp Tomsich <philipp.toms...@theobroma-systems.com> wrote: > The '*tb<optab><mode>1' can safely be extended to match operands of > any size, as long as the immediate operand (i.e. the bits tested) > match the size of the register operand. > > This removes unnecessary zero-extension operations from the > generated instruction stream.
Can you add a testcase or two for this? Thanks, Andrew > --- > gcc/config/aarch64/aarch64.md | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index b972a1b..90f1ee9 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -382,14 +382,14 @@ > > (define_insn "*tb<optab><mode>1" > [(set (pc) (if_then_else > - (EQL (zero_extract:DI (match_operand:GPI 0 "register_operand" > "r") > + (EQL (zero_extract:DI (match_operand:ALLI 0 "register_operand" > "r") > (const_int 1) > (match_operand 1 "const_int_operand" "n")) > (const_int 0)) > (label_ref (match_operand 2 "" "")) > (pc))) > (clobber (match_scratch:DI 3 "=r"))] > - "" > + "(UINTVAL(operands[1]) < GET_MODE_BITSIZE(<MODE>mode))" > "* > if (get_attr_length (insn) == 8) > return \"ubfx\\t%<w>3, %<w>0, %1, #1\;<cbz>\\t%<w>3, %l2\"; > -- > 1.9.0 >
