Hello,
Thanks a lot for all reviews!
On 09 Oct 14:55, Richard Henderson wrote:
> On 10/09/2013 03:28 AM, Kirill Yukhin wrote:
> > +;; CPUID bit AVX512F enables evex encoded scalar and 512-bit fma. It
> > doesn't
> > +;; care about FMA bit, so we enable fma for TARGET_AVX512F even when
> > TARGET_FMA
> > +;; and TARGET_FMA4 are both false.
>
> How do you force an evex encoding of the instruction?
>
> Do you really mean that cpuid AVX512F, !FMA will not #OP
> for a vex (but not evex) encoded version of the same insn?
Your concern is correct, but I believe it relates more to Binutils,
since it is GAS who cannot force EVEX encoding for such:
vfnmsub132ss %xmm1,%xmm2,%xmm3
Currently, from HW point of view, there're no CPUs which
feature AVX-512, but not AVX2. So, I believe we may put
a `TODO` in comment, like this:
+;; CPUID bit AVX512F enables evex encoded scalar and 512-bit fma. It doesn't
+;; care about FMA bit, so we enable fma for TARGET_AVX512F even when TARGET_FMA
+;; and TARGET_FMA4 are both false.
+;; TODO: if (AVX512F && !FMA && (we don't use regnos in 16..31 range) then for
+;; scalar FMA we'll got VEX encoded variant. We need somewhat improve
+;; GAS to allow forcing of EVEX encoding and then force it here.
Do you think it is acceptable?
--
Thanks, K
