> Yes - in fact this appears to be a general problem with RL78 interrupt > handlers. There are no instructions to push/pop the current bank > selection, so in order for nested interrupt handlers to work they would > have to do something like:
The bank select bits are in PSW, which is automatically saved as part of the hardware interrupt handling, and restored with RETI. My concern was with the registers in bank 3 - in a nested interrupt, those registers need to be saved too. > Which sure seems messy to me. Is it reasonable to say that C based > interrupt handlers cannot be nested, or would you like me to extend the > current patch to generate prologues/epilogues as suggested above ? I can't think of a good way to have gcc detect nested interrupts automatically. Perhaps some attribute that the user can use to override the pessimistic choice? > > Also, there are some hand-coded routines in libgloss/libgcc that > > manually swap banks, they'd have to be checked to see if there are > > issues there. Perhaps the G10 work there solved it already. > > There are ? I did not find any. Look in libgcc/config/rl78/mulsi3.S > > Those, plus Vinay's patch, should be OK otherwise. > > Vinay's patch was based on the RL78 backend supporting the G10 > architecture variant, which it currently does not. So I am attaching a > revised patch which includes my ISR improvements, Vinay's G10 ISR > improvements and the addition of G10 support to the RL78 backend. What > do you think of this version ? This is OK, but let's keep considering the nested interrupt question.
