Hi DJ,
* Uses register bank 3 instead of register bank 0 inside the handler.I wonder if nested interrupts will cause problems, since the second interrupt will occur with RB3 already selected.
Yes - in fact this appears to be a general problem with RL78 interrupt handlers. There are no instructions to push/pop the current bank selection, so in order for nested interrupt handlers to work they would have to do something like:
push ax ; Save AX mov psw, a ; Get the current register bank selection push ax ; Save it. [... rest of interrupt handler code ...] pop ax and a, #0x24 cmp a, #0x24 sknz sel rb3 cmp a, #0x20 sknz sel rb2 cmp a, #0x04 sknz sel rb1 cmp0 a sknz sel rb0 pop axWhich sure seems messy to me. Is it reasonable to say that C based interrupt handlers cannot be nested, or would you like me to extend the current patch to generate prologues/epilogues as suggested above ?
Also, there are some hand-coded routines in libgloss/libgcc that manually swap banks, they'd have to be checked to see if there are issues there. Perhaps the G10 work there solved it already.
There are ? I did not find any.
Those, plus Vinay's patch, should be OK otherwise.
Vinay's patch was based on the RL78 backend supporting the G10 architecture variant, which it currently does not. So I am attaching a revised patch which includes my ISR improvements, Vinay's G10 ISR improvements and the addition of G10 support to the RL78 backend. What do you think of this version ?
Cheers Nick
rl78.intr.patch.2
Description: Unix manual page
