With these patterns, we can now generate BICS in the appropriate places.
I've included test cases.
This has been run on linux and bare-metal regression tests.
OK to commit?
Cheers,
Ian
2013-04-26 Ian Bolton <ian.bol...@arm.com>
gcc/
* config/aarch64/aarch64.md (*and_one_cmpl<mode>3_compare0):
New pattern.
(*and_one_cmplsi3_compare0_uxtw): Likewise.
(*and_one_cmpl_<SHIFT:optab><mode>3_compare0): Likewise.
(*and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw): Likewise.
testsuite/
* gcc.target/aarch64/bics.c: New test.
* gcc.target/aarch64/bics2.c: Likewise.Index: gcc/testsuite/gcc.target/aarch64/bics.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/bics.c (revision 0)
+++ gcc/testsuite/gcc.target/aarch64/bics.c (revision 0)
@@ -0,0 +1,107 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+bics_si_test1 (int a, int b, int c)
+{
+ int d = a & ~b;
+
+ /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+bics_si_test2 (int a, int b, int c)
+{
+ int d = a & ~(b << 3);
+
+ /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl
3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+bics_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & ~b;
+
+ /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+bics_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & ~(b << 3);
+
+ /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl
3" } } */
+ if (d == 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+main ()
+{
+ int x;
+ s64 y;
+
+ x = bics_si_test1 (29, ~4, 5);
+ if (x != ((29 & 4) + ~4 + 5))
+ abort ();
+
+ x = bics_si_test1 (5, ~2, 20);
+ if (x != 25)
+ abort ();
+
+ x = bics_si_test2 (35, ~4, 5);
+ if (x != ((35 & ~(~4 << 3)) + ~4 + 5))
+ abort ();
+
+ x = bics_si_test2 (96, ~2, 20);
+ if (x != 116)
+ abort ();
+
+ y = bics_di_test1 (0x130000029ll,
+ ~0x320000004ll,
+ 0x505050505ll);
+
+ if (y != ((0x130000029ll & 0x320000004ll) + ~0x320000004ll + 0x505050505ll))
+ abort ();
+
+ y = bics_di_test1 (0x5000500050005ll,
+ ~0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 0x5000500052025ll)
+ abort ();
+
+ y = bics_di_test2 (0x130000029ll,
+ ~0x064000008ll,
+ 0x505050505ll);
+ if (y != ((0x130000029ll & ~(~0x064000008ll << 3))
+ + ~0x064000008ll + 0x505050505ll))
+ abort ();
+
+ y = bics_di_test2 (0x130002900ll,
+ ~0x088000008ll,
+ 0x505050505ll);
+ if (y != (0x130002900ll + 0x505050505ll))
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Index: gcc/testsuite/gcc.target/aarch64/bics2.c
===================================================================
--- gcc/testsuite/gcc.target/aarch64/bics2.c (revision 0)
+++ gcc/testsuite/gcc.target/aarch64/bics2.c (revision 0)
@@ -0,0 +1,111 @@
+/* { dg-do run } */
+/* { dg-options "-O2 --save-temps -fno-inline" } */
+
+extern void abort (void);
+
+int
+bics_si_test1 (int a, int b, int c)
+{
+ int d = a & ~b;
+
+ /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" }
} */
+ /* { dg-final { scan-assembler "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+bics_si_test2 (int a, int b, int c)
+{
+ int d = a & ~(b << 3);
+
+ /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+,
lsl 3" } } */
+ /* { dg-final { scan-assembler "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3"
} } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+typedef long long s64;
+
+s64
+bics_di_test1 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & ~b;
+
+ /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" }
} */
+ /* { dg-final { scan-assembler "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+s64
+bics_di_test2 (s64 a, s64 b, s64 c)
+{
+ s64 d = a & ~(b << 3);
+
+ /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+,
lsl 3" } } */
+ /* { dg-final { scan-assembler "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3"
} } */
+ if (d <= 0)
+ return a + c;
+ else
+ return b + d + c;
+}
+
+int
+main ()
+{
+ int x;
+ s64 y;
+
+ x = bics_si_test1 (29, ~4, 5);
+ if (x != ((29 & 4) + ~4 + 5))
+ abort ();
+
+ x = bics_si_test1 (5, ~2, 20);
+ if (x != 25)
+ abort ();
+
+ x = bics_si_test2 (35, ~4, 5);
+ if (x != ((35 & ~(~4 << 3)) + ~4 + 5))
+ abort ();
+
+ x = bics_si_test2 (96, ~2, 20);
+ if (x != 116)
+ abort ();
+
+ y = bics_di_test1 (0x130000029ll,
+ ~0x320000004ll,
+ 0x505050505ll);
+
+ if (y != ((0x130000029ll & 0x320000004ll) + ~0x320000004ll + 0x505050505ll))
+ abort ();
+
+ y = bics_di_test1 (0x5000500050005ll,
+ ~0x2111211121112ll,
+ 0x0000000002020ll);
+ if (y != 0x5000500052025ll)
+ abort ();
+
+ y = bics_di_test2 (0x130000029ll,
+ ~0x064000008ll,
+ 0x505050505ll);
+ if (y != ((0x130000029ll & ~(~0x064000008ll << 3))
+ + ~0x064000008ll + 0x505050505ll))
+ abort ();
+
+ y = bics_di_test2 (0x130002900ll,
+ ~0x088000008ll,
+ 0x505050505ll);
+ if (y != (0x130002900ll + 0x505050505ll))
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */
Index: gcc/config/aarch64/aarch64.md
===================================================================
--- gcc/config/aarch64/aarch64.md (revision 198231)
+++ gcc/config/aarch64/aarch64.md (working copy)
@@ -2708,6 +2708,35 @@ (define_insn "*<LOGICAL:optab>_one_cmpl<
[(set_attr "v8type" "logic")
(set_attr "mode" "<MODE>")])
+(define_insn "*and_one_cmpl<mode>3_compare0"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (and:GPI (not:GPI
+ (match_operand:GPI 1 "register_operand" "r"))
+ (match_operand:GPI 2 "register_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:GPI 0 "register_operand" "=r")
+ (and:GPI (not:GPI (match_dup 1)) (match_dup 2)))]
+ ""
+ "bics\\t%<w>0, %<w>2, %<w>1"
+ [(set_attr "v8type" "logics")
+ (set_attr "mode" "<MODE>")])
+
+;; zero_extend version of above
+(define_insn "*and_one_cmplsi3_compare0_uxtw"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (and:SI (not:SI
+ (match_operand:SI 1 "register_operand" "r"))
+ (match_operand:SI 2 "register_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (and:SI (not:SI (match_dup 1)) (match_dup 2))))]
+ ""
+ "bics\\t%w0, %w2, %w1"
+ [(set_attr "v8type" "logics")
+ (set_attr "mode" "SI")])
+
(define_insn "*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3"
[(set (match_operand:GPI 0 "register_operand" "=r")
(LOGICAL:GPI (not:GPI
@@ -2720,6 +2749,43 @@ (define_insn "*<LOGICAL:optab>_one_cmpl_
[(set_attr "v8type" "logic_shift")
(set_attr "mode" "<MODE>")])
+(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (and:GPI (not:GPI
+ (SHIFT:GPI
+ (match_operand:GPI 1 "register_operand" "r")
+ (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n")))
+ (match_operand:GPI 3 "register_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:GPI 0 "register_operand" "=r")
+ (and:GPI (not:GPI
+ (SHIFT:GPI
+ (match_dup 1) (match_dup 2))) (match_dup 3)))]
+ ""
+ "bics\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2"
+ [(set_attr "v8type" "logics_shift")
+ (set_attr "mode" "<MODE>")])
+
+;; zero_extend version of above
+(define_insn "*and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw"
+ [(set (reg:CC_NZ CC_REGNUM)
+ (compare:CC_NZ
+ (and:SI (not:SI
+ (SHIFT:SI
+ (match_operand:SI 1 "register_operand" "r")
+ (match_operand:QI 2 "aarch64_shift_imm_si" "n")))
+ (match_operand:SI 3 "register_operand" "r"))
+ (const_int 0)))
+ (set (match_operand:DI 0 "register_operand" "=r")
+ (zero_extend:DI (and:SI
+ (not:SI
+ (SHIFT:SI (match_dup 1) (match_dup 2))) (match_dup
3))))]
+ ""
+ "bics\\t%w0, %w3, %w1, <SHIFT:shift> %2"
+ [(set_attr "v8type" "logics_shift")
+ (set_attr "mode" "SI")])
+
(define_insn "clz<mode>2"
[(set (match_operand:GPI 0 "register_operand" "=r")
(clz:GPI (match_operand:GPI 1 "register_operand" "r")))]
