From: Pan Li <[email protected]>
Add the test cases for the ICE of the widening insn when the nregs
of the dest is less than that of the src.
PR target/127269
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/pr127269-18.c: New test.
* gcc.target/riscv/rvv/base/pr127269-19.c: New test.
* gcc.target/riscv/rvv/base/pr127269-20.c: New test.
* gcc.target/riscv/rvv/base/pr127269-21.c: New test.
* gcc.target/riscv/rvv/base/pr127269-22.c: New test.
Signed-off-by: Pan Li <[email protected]>
---
.../gcc.target/riscv/rvv/base/pr127269-18.c | 14 ++++++++++++++
.../gcc.target/riscv/rvv/base/pr127269-19.c | 14 ++++++++++++++
.../gcc.target/riscv/rvv/base/pr127269-20.c | 14 ++++++++++++++
.../gcc.target/riscv/rvv/base/pr127269-21.c | 14 ++++++++++++++
.../gcc.target/riscv/rvv/base/pr127269-22.c | 14 ++++++++++++++
5 files changed, 70 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-18.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-19.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-20.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-21.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-22.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-18.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-18.c
new file mode 100644
index 00000000000..804d66c0707
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-18.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */
+/* PR target/127269 */
+
+#include "riscv_vector.h"
+
+/* This test is to ensure there is no ICE during compilation. */
+
+vint32m2_t
+test (vint16m4_t a, vint32m2_t b, size_t vl)
+{
+ vint16m1_t c = __riscv_vget_v_i16m4_i16m1 (a, 0);
+ return __riscv_vwmacc_vx_i32m2 (b, 1, c, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-19.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-19.c
new file mode 100644
index 00000000000..a67959418d9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-19.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */
+/* PR target/127269 */
+
+#include "riscv_vector.h"
+
+/* This test is to ensure there is no ICE during compilation. */
+
+vint32m2_t
+test (vint16m8_t a, size_t vl)
+{
+ vint16m1_t b = __riscv_vget_v_i16m8_i16m1 (a, 3);
+ return __riscv_vwmul_vv_i32m2 (b, b, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-20.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-20.c
new file mode 100644
index 00000000000..d199000d19f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-20.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */
+/* PR target/127269 */
+
+#include "riscv_vector.h"
+
+/* This test is to ensure there is no ICE during compilation. */
+
+vint16m2_t
+test (vint8m8_t a, size_t vl)
+{
+ vint8m1_t b = __riscv_vget_v_i8m8_i8m1 (a, 2);
+ return __riscv_vsext_vf2_i16m2 (b, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-21.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-21.c
new file mode 100644
index 00000000000..d893ebdf1b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-21.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O2" } */
+/* PR target/127269 */
+
+#include "riscv_vector.h"
+
+/* This test is to ensure there is no ICE during compilation. */
+
+vfloat32m2_t
+test (vfloat16m4_t a, size_t vl)
+{
+ vfloat16m1_t b = __riscv_vget_v_f16m4_f16m1 (a, 1);
+ return __riscv_vfwcvt_f_f_v_f32m2 (b, vl);
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-22.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-22.c
new file mode 100644
index 00000000000..29e4d770644
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-22.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */
+/* PR target/127269 */
+
+#include "riscv_vector.h"
+
+/* This test is to ensure there is no ICE during compilation. */
+
+vuint64m4_t
+test (vuint32m8_t a, vuint64m4_t b, size_t vl)
+{
+ vuint32m2_t c = __riscv_vget_v_u32m8_u32m2 (a, 1);
+ return __riscv_vwaddu_wv_u64m4 (b, c, vl);
+}
--
2.43.0
