From: Pan Li <[email protected]>

The lra may try the mode like RVVM4SImode, and RVVM2HImode of widen
mode to riscv_v_widen_constraint_ok.  Therefore reject that combination
instead of assertion.

The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.

Pan Li (2):
  RISC-V: Fix ICE for widening insn when dest nregs is less than src [PR 
target/127269]
  RISC-V: Add test cases for widening insn ICE [PR target/127269]

 gcc/config/riscv/riscv-v.cc                        |  3 ++-
 .../gcc.target/riscv/rvv/base/pr127269-18.c        | 14 ++++++++++++++
 .../gcc.target/riscv/rvv/base/pr127269-19.c        | 14 ++++++++++++++
 .../gcc.target/riscv/rvv/base/pr127269-20.c        | 14 ++++++++++++++
 .../gcc.target/riscv/rvv/base/pr127269-21.c        | 14 ++++++++++++++
 .../gcc.target/riscv/rvv/base/pr127269-22.c        | 14 ++++++++++++++
 6 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-18.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-19.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-20.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-21.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr127269-22.c

-- 
2.43.0

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