Hi Bohan,
> +(define_mode_iterator VWEXTI_HS [
> + RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_VECTOR_ELEN_64")
> +
> + RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_VECTOR_ELEN_64")
> +
> + (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)")
> + (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)")
> + (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)")
> + (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)")
> + (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)")
> + (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >=
> 64")
> + (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >=
> 128")
> + (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >=
> 256")
> + (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >=
> 512")
> + (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >=
> 1024")
> + (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN
> >= 2048")
> + (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN
> >= 4096")
> + (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
> + (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
> + (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
> + (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
> + (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >=
> 64")
> + (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >=
> 128")
> + (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >=
> 256")
> + (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >=
> 512")
> + (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >=
> 1024")
> + (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >=
> 2048")
> + (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN
> >= 4096")
> +])
> +
> (define_mode_iterator VWEXTI_D [
> (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
> (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
> @@ -5898,6 +5928,8 @@ (define_mode_iterator V_VLSI_S [
> (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN
> >= 4096")
> ])
Is VWEXTI = VWEXTI_HS + VWEXTI_D? I guess it should :) Can we combine
it?
> +(define_mode_iterator V_VLSI_SD [V_VLSI_S V_VLSI_D])
> +
Leftover?
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvabd-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvabd-2.c
> new file mode 100644
> index 00000000000..a3e624d8362
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/zvabd-2.c
> +
> +/* { dg-final { scan-assembler-not {vabd\.vv} } } */
> +/* { dg-final { scan-assembler-not {vwabda\.vv} } } */
Can you fold these into zvabd-1.c? Add the unsupported types to
TEST_ALL and keep the assembler tests the same.
Of course execution tests would be nice as well. I'd say not in scope
for this fix but generally desirable. That would be a somewhat
larger change due to the necessary testsuite/dejagnu boilerplate.
The rest looks good to me.
--
Regards
Robin
