[PATCH 7/9] RISC-V: Add minimal Ssctr extension support

[Jiawei]

This adds minimal support for the Ssctr[1] (Supervisor-mode control transfer
records) extension, which depends on Zicsr.



gcc/ChangeLog:

        * config/riscv/riscv-ext.def (ssctr): Add new extension.
        * config/riscv/riscv-ext.opt: Ditto.
        * doc/riscv-ext.texi: Ditto.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/ssctr-version.c: New test.

---
 gcc/config/riscv/riscv-ext.def                 | 13 +++++++++++++
 gcc/config/riscv/riscv-ext.opt                 |  2 ++
 gcc/doc/riscv-ext.texi                         |  4 ++++
 gcc/testsuite/gcc.target/riscv/ssctr-version.c | 15 +++++++++++++++
 4 files changed, 34 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/ssctr-version.c

diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index ddcd8ae1620..9362a8e2412 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -1962,6 +1962,19 @@ DEFINE_RISCV_EXT(
   /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
   /* EXTRA_EXTENSION_FLAGS */ 0)
 
+DEFINE_RISCV_EXT(
+  /* NAME */ ssctr,
+  /* UPPERCASE_NAME */ SSCTR,
+  /* FULL_NAME */ "Supervisor-mode control transfer records extension",
+  /* DESC */ "",
+  /* URL */ ,
+  /* DEP_EXTS */ ({"zicsr"}),
+  /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+  /* FLAG_GROUP */ ss,
+  /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+  /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+  /* EXTRA_EXTENSION_FLAGS */ 0)
+
 DEFINE_RISCV_EXT(
   /* NAME */ sscsrind,
   /* UPPERCASE_NAME */ SSCSRIND,
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index fef5fe1d867..f967236d3c8 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -391,6 +391,8 @@ Mask(SSCOFPMF) Var(riscv_ss_subext)
 
 Mask(SSCOUNTERENW) Var(riscv_ss_subext)
 
+Mask(SSCTR) Var(riscv_ss_subext)
+
 Mask(SSCSRIND) Var(riscv_ss_subext)
 
 Mask(SSNPM) Var(riscv_ss_subext)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 2e2a6619579..94fd71ad82a 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -582,6 +582,10 @@
 @tab 1.0
 @tab Support writeable enables for any supported counter
 
+@item @samp{ssctr}
+@tab 1.0
+@tab Supervisor-mode control transfer records extension
+
 @item @samp{sscsrind}
 @tab 1.0
 @tab Supervisor-mode indirect CSR access
diff --git a/gcc/testsuite/gcc.target/riscv/ssctr-version.c 
b/gcc/testsuite/gcc.target/riscv/ssctr-version.c
new file mode 100644
index 00000000000..4d119360df5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/ssctr-version.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-mriscv-attribute -march=rv64i_ssctr1p0 -mabi=lp64" { target 
{ rv64 } } } */
+/* { dg-options "-mriscv-attribute -march=rv32i_ssctr1p0 -mabi=ilp32" { target 
{ rv32 } } } */
+
+#ifndef __riscv_ssctr
+#error "Feature macro for 'ssctr' not defined"
+#endif
+
+int
+foo (void)
+{
+  return 0;
+}
+
+/* { dg-final { scan-assembler ".attribute arch, .*ssctr1p0" } } */
-- 
2.43.0