> The x86 backend transitioned to UNSPECs for masked loads/stores because
> of correctness issues, so IMO getting RTL semantics correct is important.
>
> Note that the flat (vec_predicate ...) feels a lot like an UNSPEC and
> we have to avoid making the actual semantics target dependent.
I can't really think of a nice way of expressing predicated stores that would
fit the other variants we discussed.
Too last-ditch ideas are either a (subreg (mem)) like abomination:
(set (vec_predicate/cond_exec/... (mem ...))
where the entire predicate is on the LHS or a separate "thing" altogether:
(vec_predicated_store
mem
val
mask
len
...)
--
Regards
Robin
