gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_hard_regno_nregs): Handle
`FP_HI_REGS`.
(aarch64_class_max_nregs): Likewise.
* config/aarch64/aarch64.h (reg_class::FP_HI_REGS): New enum member.
* config/aarch64/constraints.md (z): New register constraint.
(Ux2): Likewise.
(Uxz): Likewise.
---
gcc/config/aarch64/aarch64.cc | 2 ++
gcc/config/aarch64/aarch64.h | 3 +++
gcc/config/aarch64/constraints.md | 11 +++++++++++
3 files changed, 16 insertions(+)
diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 0ef22e8e52c..9d7e20d8413 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -2195,6 +2195,7 @@ aarch64_hard_regno_nregs (unsigned regno, machine_mode
mode)
case FP_REGS:
case FP_LO_REGS:
case FP_LO8_REGS:
+ case FP_HI_REGS:
{
unsigned int vec_flags = aarch64_classify_vector_mode (mode);
if (vec_flags & VEC_SVE_DATA)
@@ -13824,6 +13825,7 @@ aarch64_class_max_nregs (reg_class_t regclass,
machine_mode mode)
case FP_REGS:
case FP_LO_REGS:
case FP_LO8_REGS:
+ case FP_HI_REGS:
vec_flags = aarch64_classify_vector_mode (mode);
if ((vec_flags & VEC_SVE_DATA)
&& constant_multiple_p (GET_MODE_SIZE (mode),
diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index 540dfd00190..9d6f3fef7c2 100644
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -867,6 +867,7 @@ enum reg_class
POINTER_REGS,
FP_LO8_REGS,
FP_LO_REGS,
+ FP_HI_REGS,
FP_REGS,
POINTER_AND_FP_REGS,
PR_LO_REGS,
@@ -894,6 +895,7 @@ enum reg_class
"POINTER_REGS", \
"FP_LO8_REGS", \
"FP_LO_REGS", \
+ "FP_HI_REGS", \
"FP_REGS", \
"POINTER_AND_FP_REGS", \
"PR_LO_REGS", \
@@ -918,6 +920,7 @@ enum reg_class
{ 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \
{ 0x00000000, 0x000000ff, 0x00000000 }, /* FP_LO8_REGS */ \
{ 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \
+ { 0x00000000, 0xffff0000, 0x00000000 }, /* FP_HI_REGS */ \
{ 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \
{ 0xffffffff, 0xffffffff, 0x00000003 }, /* POINTER_AND_FP_REGS */\
{ 0x00000000, 0x00000000, 0x00000ff0 }, /* PR_LO_REGS */ \
diff --git a/gcc/config/aarch64/constraints.md
b/gcc/config/aarch64/constraints.md
index b84993efb7f..89352c54418 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -48,6 +48,17 @@ (define_register_constraint "x" "FP_LO_REGS"
(define_register_constraint "y" "FP_LO8_REGS"
"SVE/NEON/FP registers, V0 - V7.")
+(define_register_constraint "z" "FP_HI_REGS"
+ "SVE/NEON/FP registers, V16 - V31.")
+
+(define_register_constraint "Ux2" "FP_LO_REGS"
+ "Even SVE/NEON/FP registers, V0, V2, ..., V14."
+ "regno % 2 == 0")
+
+(define_register_constraint "Uz2" "FP_HI_REGS"
+ "Even SVE/NEON/FP registers, V16, V18, ..., V30."
+ "regno % 2 == 0")
+
(define_register_constraint "Uw2" "FP_REGS"
"Even SVE/NEON/FP registers, V0, V2, ..., V30."
"regno % 2 == 0")
--
2.43.0
